
MPC509
User’s Manual
INDEX
MOTOROLA
Index-5
Rev. 15 June 1998
IRQ 2-21, 6-10
IRQAND 6-8, 6-9
IRQENABLE 6-8, 6-9
IRQMUX 6-3, 6-8
IRQPEND 6-8, 6-9
ISCTL 5-30, 8-1
ISE 8-54
ISEE 8-55
ITYPE 5-44, 5-52, 5-53
IU 3-5
IW 8-48
–J–
Joint test action group. See JTAG
JTAG 9-1
instruction register 9-3
non-IEEE 1149.1-1990 operation 9-8
reset 5-93
signals 9-1, 9-2
–L–
LAST 5-5, 5-23, 5-53, 5-54, 5-63
LBRK 8-54
L-bus 5-7
IMB2 interface 5-7
memory 5-30
enable 5-6
show cycles 5-5
to I-bus cross bus access enable 5-6
L-bus support 8-17
control register 1 8-49
control register 2 8-50
LCK 7-3
LCTRL1 8-49
LCTRL2 8-50
LE bit 3-19
LEN 5-6
LIMB 5-7
Link register 3-16
Little endian mode 3-19
LIX 5-6, 5-11
LMEMBASE 5-6, 5-8, 7-1
Load and lock 4-7
Load/store unit 3-5, 3-6
Lock bits and freeze assertion 5-12
Lock, PLL 5-93
status 5-82
LOK 5-5, 5-38
LOL 5-93
LOLRE 5-76, 5-82, 5-83
LOO 5-82, 5-85, 5-93
Loop filter 5-73
LOORE 5-82, 5-83
Loss of oscillator 5-93
reset enable 5-82, 5-83
status 5-85
Loss of PLL lock 5-93
reset enable 5-76, 5-82, 5-83
Low-power mode 5-78
lock 5-85
mask 5-83
select bits 5-84
LPM 5-78, 5-84
LPML 5-78, 5-80, 5-85
LPMM 5-79, 5-83
LR 3-5, 3-16
LSHOW 5-5
LST 5-5, 5-23
LSU 3-5, 3-6
LW0EN 8-51
LW0IA 8-51
LW0IADC 8-51
LW0LA 8-51
LW0LADC 8-51
LW0LD 8-51
LW0LDDC 8-51
LW1EN 8-51
LW1IA 8-51
LW1IADC 8-51
LW1LA 8-51
LW1LADC 8-51
LW1LD 8-51
LW1LDDC 8-51
lwarx 5-31
–M–
Machine
check enable 3-19
check exception 5-28, 5-48
state register 3-18
status save/restore register 0 3-21
status save/restore register 1 3-22
MASK 5-26
MASKNUM 5-5
MCE 8-54
MCEE 8-55
ME bit 3-19
MEMMAP 5-6, 5-8, 5-10
Memory
block mapping 5-8
mapping register. See MEMMAP
regions 5-44
Memory regions 5-44
MF 5-74, 5-75, 5-83
lock bit 5-76, 5-85
MFD 5-74
MODCLK 2-19, 5-70
Module select logic 5-7
MPL 5-76, 5-80, 5-85
MSR 3-18
Multi-level protection 5-46
Multiplication factor 5-74, 5-75, 5-83
divider 5-74
–N–
NI bit 3-13
Non-IEEE 1149.1-1990 operation 9-8
Non-IEEE floating-point operation 3-13