參數(shù)資料
型號(hào): MCIMX537CVV8C
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 800 MHz, RISC PROCESSOR, PBGA529
封裝: 19 X 19 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, TEPBGA-529
文件頁數(shù): 84/172頁
文件大?。?/td> 4562K
代理商: MCIMX537CVV8C
Electrical Characteristics
i.MX53 Applications Processors for Industrial Products, Rev. 3
Freescale Semiconductor
19
NVCC_NANDF
NVCC_SD1
NVCC_SD2
NVCC_PATA
NVCC_KEYPAD
NVCC_GPIO
NVCC_FEC
NVCC_EIM_MAIN
NVCC_EIM_SEC
NVCC_CSI
Ultra High voltage I/O (UHVIO) supplies:
V
UHVIO_L
1.65
1.8
1.95
UHVIO_H
2.5
2.775
3.1
UHVIO_UH
3.0
3.3
3.6
TVDAC_DHVDD8
TVDAC_AHVDDRGB8
TVE digital and analog power supply, TVE-to-DAC
level shifter supply, cable detector supply, analog
power supply to RGB channel
2.69
2.75
2.91
V
For GPIO use only, when TVE is not in use
1.65
1.8 or
2.775
3.1
V
NVCC_SRTC_POW
SRTC Core and slow I/O Supply (GPIO)9
1.25
1.3
1.35
V
NVCC_RESET
LVIO
1.65
1.8 or
2.775
3.1
V
USB_H1_VDDA25
USB_OTG_VDDA25
NVCC_XTAL
USB_PHY analog supply, oscillator amplifier analog
supply10
2.25
2.5
2.75
V
USB_H1_VDDA33
USB_OTG_VDDA33
USB PHY I/O analog supply
3.0
3.3
3.6
V
VBUS
for details. Note that this is not a power supply.
——
VDD_REG11
Power supply input for the integrated linear
regulators
2.37
2.5
2.63
V
VP
SATA PHY core power supply
1.25
1.3
1.35
V
VPH
SATA PHY I/O supply voltage
2.25
2.5
2.75
V
TJ
Junction Temperature
–40
10512
125
oC
1 Voltage at the package power supply contact must be maintained between the minimum and maximum voltages. The design
must allow for supply tolerances and system voltage drops.
2 The nominal values for the supplies indicate the target setpoint for a tolerance no tighter than ± 50 mV. Use of supplies with a
tighter tolerance allows reduction of the setpoint with commensurate power savings.
3 A voltage transition is allowed for the required supply ramp up to the nominal value prior to achieving a clock speed increase.
Similarly, to accommodate a frequency reduction, a voltage transition is allowed for a supply ramp down to the nominal value
after the frequency is decreased.
4 VDDA and VDDAL1 can be driven by the VDD_DIG_PLL internal regulator using external connections. When operating in this
configuration, the regulator is still operating at the default 1.2 V, as bootup start. During bootup initialization, software should
increase this regulator voltage to match VCC (1.3 V nominal) in order to reduce internal leakage current.
5 By default, VDD_DIG_PLL is driven from internal on-die 1.2 V linear regulator (LDO). In this case, there is no need driving this
supply externally. LDO output to VDD_DIG_PLL should be configured by software after power-up to 1.3 V output. A bypass
capacitor of minimal value 22
μF should be connected to this pad in any case whether it is driven internally or externally. Use
of the on-chip LDO is preferred. See i.MX53 System Development User’s Guide.
Table 6. i.MX53 Operating Ranges (continued)
Symbol
Parameter
Minimum1 Nominal2 Maximum1
Unit
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參數(shù)描述
MCIMX537CVV8C 制造商:Freescale Semiconductor 功能描述:IC 32-BIT MPU 800 MHZ 529-BGA
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MCIMX53EVK 制造商:Freescale Semiconductor 功能描述:
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