參數(shù)資料
型號: MCIMX537CVV8C
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 800 MHz, RISC PROCESSOR, PBGA529
封裝: 19 X 19 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, TEPBGA-529
文件頁數(shù): 149/172頁
文件大?。?/td> 4562K
代理商: MCIMX537CVV8C
i.MX53 Applications Processors for Industrial Products, Rev. 3
78
Freescale Semiconductor
Electrical Characteristics
.
Figure 39. MII Transmit Signal Timing Diagram
4.7.5.3
MII Async Inputs Signal Timing (FEC_CRS and FEC_COL)
Table 53 lists MII asynchronous inputs signal timing information. Figure 40 shows MII asynchronous
input timings listed in Table 53.
.
Figure 40. MII Async Inputs Timing Diagram
4.7.5.4
MII Serial Management Channel Timing (FEC_MDIO and FEC_MDC)
Table 54 lists MII serial management channel timings. Figure 41 shows MII serial management channel
timings listed in Table 54. The MDC frequency should be equal to or less than 2.5 MHz to be compliant
with the IEEE 802.3 MII specification. However, the FEC can function correctly with a maximum MDC
frequency of 15 MHz.
Table 53. MII Async Inputs Signal Timing
Num
Characteristic 1
1 Test conditions: 25pF on each output signal.
Min
Max
Unit
M92
2 FEC_COL has the same timing in 10 Mbit 7-wire interface mode.
FEC_CRS to FEC_COL minimum pulse width
1.5
FEC_TX_CLK period
Table 54. MII Transmit Signal Timing
ID
Characteristics1
Min
Max
Unit
M10
FEC_MDC falling edge to FEC_MDIO output invalid (minimum propagation delay)
0
ns
M11
FEC_MDC falling edge to FEC_MDIO output valid (max propagation delay)
5
ns
M12
FEC_MDIO (input) to FEC_MDC rising edge setup
18
ns
FEC_TX_CLK (input)
FEC_TXD[3:0] (outputs)
FEC_TX_EN
FEC_TX_ER
M7
M8
M5
M6
FEC_CRS, FEC_COL
M9
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