參數(shù)資料
型號(hào)： MCIMX537CVV8C
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 800 MHz, RISC PROCESSOR, PBGA529
封裝： 19 X 19 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, TEPBGA-529
文件頁數(shù)： 156/172頁
文件大?。?/td> 4562K
代理商： MCIMX537CVV8C
i.MX53 Applications Processors for Industrial Products, Rev. 3
84
Freescale Semiconductor
Electrical Characteristics
SENSB_HSYNC goes to low at the end of line. Pixel clocks then become invalid and the CSI stops
receiving data from the stream. For next line the SENSB_HSYNC timing repeats. For next frame the
SENSB_VSYNC timing repeats.
4.7.8.2.3
Non-Gated Clock Mode
The timing is the same as the gated-clock mode (described in Section 4.7.8.2.2, “Gated Clock Mode,”)
except for the SENSB_HSYNC signal, which is not used (see Figure 45). All incoming pixel clocks are
valid and cause data to be latched into the input FIFO. The SENSB_PIX_CLK signal is inactive (states
low) until valid data is going to be transmitted over the bus.
Figure 45. Non-Gated Clock Mode Timing Diagram
The timing described in Figure 45 is that of a typical sensor. Some other sensors may have a slightly
different timing. The CSI can be programmed to support rising/falling-edge triggered SENSB_VSYNC;
active-high/low SENSB_HSYNC; and rising/falling-edge triggered SENSB_PIX_CLK.
4.7.8.3
Electrical Characteristics
Figure 46 depicts the sensor interface timing. SENSB_MCLK signal described here is not generated by
the IPU. Table 58 lists the sensor interface timing characteristics.
Figure 46. Sensor Interface Timing Diagram
SENSB_VSYNC
SENSB_PIX_CLK
SENSB_DATA[19:0]
invalid
1st byte
n+1th frame
invalid
1st byte
nth frame
Start of Frame
IP3
SENSB_DATA,
SENSB_VSYNC,
IP2
1/IP1
SENSB_PIX_CLK
(Sensor Output)
SENSB_HSYNC
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MCIMX537CVV8C 制造商:Freescale Semiconductor 功能描述:IC 32-BIT MPU 800 MHZ 529-BGA
MCIMX537CVV8CR2 功能描述:處理器 - 專門應(yīng)用 iMX53 Rev 2.1 Indust RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
MCIMX538DZK1C 功能描述:處理器 - 專門應(yīng)用 I.MX53 2.1 POP RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
MCIMX53EVK 制造商:Freescale Semiconductor 功能描述:
MCIMX53-LVDS 制造商:Freescale Semiconductor 功能描述:I.MX53 XGA DISPLAY LVDS DEV BOARD 制造商:Freescale Semiconductor 功能描述:I.MX53, XGA DISPLAY, LVDS, DEV BOARD 制造商:Freescale Semiconductor 功能描述:I.MX53, XGA DISPLAY, LVDS CONNECTOR, DEV BOARD; Silicon Manufacturer:Freescale; Core Architecture:ARM; Core Sub-Architecture:Cortex-A8; Silicon Core Number:i.MX5; Silicon Family Name:i.MX53
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