參數資料
型號： MCIMX537CVV8C
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 800 MHz, RISC PROCESSOR, PBGA529
封裝： 19 X 19 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, TEPBGA-529
文件頁數： 153/172頁
文件大?。?/td> 4562K
代理商： MCIMX537CVV8C
Electrical Characteristics
i.MX53 Applications Processors for Industrial Products, Rev. 3
Freescale Semiconductor
81
4.7.7
I2C Module Timing Parameters
This section describes the timing parameters of the I2C module. Figure 43 depicts the timing of I2C
module, and Table 56 lists the I2C module timing characteristics.
Figure 43. I2C Bus Timing
Table 56. I2C Module Timing Parameters
ID
Parameter
Standard Mode
Supply Voltage =
1.65 V–1.95 V, 2.7 V–3.3 V
Fast Mode
Supply Voltage =
2.7 V–3.3 V
Unit
Min
Max
Min
Max
IC1
I2CLK cycle time
10
—
2.5
—
s
IC2
Hold time (repeated) START condition
4.0
—
0.6
—
s
IC3
Set-up time for STOP condition
4.0
—
0.6
—
s
IC4
Data hold time
01
1 A device must internally provide a hold time of at least 300 ns for I2DAT signal in order to bridge the undefined region of the
falling edge of I2CLK.
3.452
2 The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2CLK signal.
0.92
s
IC5
HIGH Period of I2CLK Clock
4.0
—
0.6
—
s
IC6
LOW Period of the I2CLK Clock
4.7
—
1.3
—
s
IC7
Set-up time for a repeated START condition
4.7
—
0.6
—
s
IC8
Data set-up time
250
—
1003
3 A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement of Set-up time (ID No IC7)
of 250 ns must be met. This automatically is the case if the device does not stretch the LOW period of the I2CLK signal.
If such a device does stretch the LOW period of the I2CLK signal, it must output the next data bit to the I2DAT line
max_rise_time (IC9) + data_setup_time (IC7) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification)
before the I2CLK line is released.
—ns
IC9
Bus free time between a STOP and START condition
4.7
—
1.3
—
s
IC10
Rise time of both I2DAT and I2CLK signals
—
1000
20 + 0.1Cb
4
4 C
b = total capacitance of one bus line in pF.
300
ns
IC11
Fall time of both I2DAT and I2CLK signals
—
300
20 + 0.1Cb
300
ns
IC12
Capacitive load for each bus line (Cb)
—
400
—
400
pF
IC10
IC11
IC9
IC2
IC8
IC4
IC7
IC3
IC6
IC10
IC5
IC11
START
STOP
START
I2DAT
I2CLK
IC1
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相關代理商/技術參數
參數描述
MCIMX537CVV8C 制造商:Freescale Semiconductor 功能描述:IC 32-BIT MPU 800 MHZ 529-BGA
MCIMX537CVV8CR2 功能描述:處理器 - 專門應用 iMX53 Rev 2.1 Indust RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數據總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數據緩存: 數據 RAM 大小:128 KB 數據 ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風格:SMD/SMT 封裝 / 箱體:MAPBGA-432
MCIMX538DZK1C 功能描述:處理器 - 專門應用 I.MX53 2.1 POP RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數據總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數據緩存: 數據 RAM 大小:128 KB 數據 ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風格:SMD/SMT 封裝 / 箱體:MAPBGA-432
MCIMX53EVK 制造商:Freescale Semiconductor 功能描述:
MCIMX53-LVDS 制造商:Freescale Semiconductor 功能描述:I.MX53 XGA DISPLAY LVDS DEV BOARD 制造商:Freescale Semiconductor 功能描述:I.MX53, XGA DISPLAY, LVDS, DEV BOARD 制造商:Freescale Semiconductor 功能描述:I.MX53, XGA DISPLAY, LVDS CONNECTOR, DEV BOARD; Silicon Manufacturer:Freescale; Core Architecture:ARM; Core Sub-Architecture:Cortex-A8; Silicon Core Number:i.MX5; Silicon Family Name:i.MX53
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