參數(shù)資料
型號(hào)： MCIMX537CVV8C
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 800 MHz, RISC PROCESSOR, PBGA529
封裝： 19 X 19 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, TEPBGA-529
文件頁數(shù)： 13/172頁
文件大?。?/td> 4562K
代理商： MCIMX537CVV8C
Modules List
i.MX53 Applications Processors for Industrial Products, Rev. 3
Freescale Semiconductor
11
OWIRE
One-Wire
Interface
Connectivity
Peripherals
One-wire support provided for interfacing with an on-board EEPROM, and
smart battery interfaces, for example, Dallas DS2502.
PATA
Parallel ATA
Connectivity
Peripherals
The PATA block is a AT attachment host interface. Its main use is to interface
with hard disk drives and optical disc drives. It interfaces with the ATA-6
compliant device over a number of ATA signals. It is possible to connect a
bus buffer between the host side and the device side.
PWM-1
PWM-2
Pulse Width
Modulation
Connectivity
Peripherals
The pulse-width modulator (PWM) has a 16-bit counter and is optimized to
generate sound from stored sample audio images. It can also generate
tones. The PWM uses 16-bit resolution and a 4 x 16 data FIFO to generate
sound.
INTRAM
Internal RAM
Internal
Memory
Internal RAM, shared with VPU.
The on-chip memory controller (OCRAM) module, is an interface between
the system’s AXI bus, to the internal (on-chip) SRAM memory module. It is
used for controlling the 128 KB multimedia RAM, through a 64-bit AXI bus.
BOOTROM
Boot ROM
Internal
Memory
Supports secure and regular boot modes.
The ROM controller supports ROM patching.
RTIC
Run-Time
Integrity Checker
Security
Protecting read only data from modification is one of the basic elements in
trusted platforms. The run-time integrity checker, version 3 (RTIC) block is
a data-monitoring device responsible for ensuring that the memory content
is not corrupted during program execution. The RTIC mechanism
periodically checks the integrity of code or data sections during normal OS
run-time execution without interfering with normal operation. The purpose
of the RTIC is to ensure the integrity of the peripheral memory contents,
protect against unauthorized external memory elements replacement and
assist with boot authentication.
SAHARA
Security
Accelerator
Security
SAHARA (symmetric/asymmetric hashing and random accelerator),
version 4, is a security coprocessor. It implements symmetric encryption
algorithms, (AES, DES, 3DES, RC4 and C2), public key algorithms (RSA
and ECC), hashing algorithms (MD5, SHA-1, SHA-224 and SHA-256), and
a hardware true random number generator. It has a slave IP Bus interface
for the host to write configuration and command information, and to read
status information. It also has a DMA controller, with an AHB bus interface,
to reduce the burden on the host to move the required data to and from
memory.
SATA
Serial ATA
Connectivity
Peripherals
SATA HDD interface, includes the SATA controller and the PHY. It is a
complete mixed-signal IP solution for SATA HDD connectivity.
SCCv2
Security
Controller, ver. 2
Security
The security controller is a security assurance hardware module designed
to safely hold sensitive data, such as encryption keys, digital right
management (DRM) keys, passwords and biometrics reference data. The
SCCv2 monitors the system’s alert signal to determine if the data paths to
and from it are secure, that is, it cannot be accessed from outside of the
defined security perimeter. If not, it erases all sensitive data on its internal
RAM. The SCCv2 also features a key encryption module (KEM) that allows
non-volatile (external memory) storage of any sensitive data that is
temporarily not in use. The KEM utilizes a device-specific hidden secret key
and a symmetric cryptographic algorithm to transform the sensitive data
into encrypted data.
Table 2. i.MX53 Digital and Analog Blocks (continued)
Block
Mnemonic
Block Name
Subsystem
Brief Description
相關(guān)PDF資料
PDF描述
MCM16Y1BACFT16 16-BIT, MROM, MICROCONTROLLER, PQFP160
MCM16Y1BGCFT16 16-BIT, MROM, MICROCONTROLLER, PQFP160
M68HC16Y1CFC 16-BIT, MROM, MICROCONTROLLER, PQFP16
MCV14AI/SL 8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PDSO14
MCV14ATI/SL 8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PDSO14
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MCIMX537CVV8C 制造商:Freescale Semiconductor 功能描述:IC 32-BIT MPU 800 MHZ 529-BGA
MCIMX537CVV8CR2 功能描述:處理器 - 專門應(yīng)用 iMX53 Rev 2.1 Indust RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
MCIMX538DZK1C 功能描述:處理器 - 專門應(yīng)用 I.MX53 2.1 POP RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
MCIMX53EVK 制造商:Freescale Semiconductor 功能描述:
MCIMX53-LVDS 制造商:Freescale Semiconductor 功能描述:I.MX53 XGA DISPLAY LVDS DEV BOARD 制造商:Freescale Semiconductor 功能描述:I.MX53, XGA DISPLAY, LVDS, DEV BOARD 制造商:Freescale Semiconductor 功能描述:I.MX53, XGA DISPLAY, LVDS CONNECTOR, DEV BOARD; Silicon Manufacturer:Freescale; Core Architecture:ARM; Core Sub-Architecture:Cortex-A8; Silicon Core Number:i.MX5; Silicon Family Name:i.MX53
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