參數(shù)資料
型號(hào): MCIMX537CVV8C
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 800 MHz, RISC PROCESSOR, PBGA529
封裝: 19 X 19 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, TEPBGA-529
文件頁數(shù): 120/172頁
文件大?。?/td> 4562K
代理商: MCIMX537CVV8C
Electrical Characteristics
i.MX53 Applications Processors for Industrial Products, Rev. 3
Freescale Semiconductor
51
4.6.6
External Interface Module (EIM)
The following subsections provide information on the EIM.
4.6.6.1
EIM Signal Cross Reference
Table 36 is a guide intended to help the user identify signals in the External Interface Module Chapter of
the Reference Manual which are identical to those mentioned in this data sheet.
4.6.6.2
EIM Interface Pads Allocation
EIM supports16-bit and 8-bit devices operating in address/data separate or multiplexed modes. In some
of the modes the EIM and the NAND FLASH have shared data bus. Table 37 provides EIM interface
pads allocation in different modes.
4 NF17 is defined only in asymmetric operation mode.
NF17 max value is equivalent to max tRHZ value that can be used with NFC.
Taclk is “emi_slow_clk” of the system.
5
NF18 is defined only in Symmetric operation mode.
tDHR (MIN) is calculated by the following formula:
Tdl2 – (tREpd + tDpd)
where tREpd is RE propogation delay in the chip including I/O pad delay, and tDpd is Data propogation delay from I/O pad to
EXTMC including I/O pad delay.
NF18 max value is equivalent to max tRHZ value that can be used with NFC.
Taclk is “emi_slow_clk” of the system.
Table 36. EIM Signal Cross Reference
Reference Manual
EIM Chapter Nomenclature
Data Sheet Nomenclature,
Reference Manual External Signals and Pin Multiplexing Chapter,
and IOMUXC Controller Chapter Nomenclature
BCLK
EIM_BCLK
CSx
EIM_CSx
WE_B
EIM_RW
OE_B
EIM_OE
BEy_B
EIM_EBx
ADV
EIM_LBA
ADDR
EIM_A[25:16], EIM_DA[15:0]
ADDR/M_DATA
EIM_DAx (Addr/Data muxed mode)
DATA
EIM_NFC_D (Data bus shared with NAND Flash)
EIM_Dx (dedicated data bus)
WAIT_B
EIM_WAIT
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