參數(shù)資料
型號： MCC68HC711D3
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, UUC
封裝： DIE
文件頁數(shù)： 82/157頁
文件大?。?/td> 2252K
代理商： MCC68HC711D3
Operating Modes and Memory
Data Sheet
MC68HC711D3 — Rev. 2
30
Operating Modes and Memory
MOTOROLA
2.3.2 RAM and I/O Mapping Register
The random-access memory (RAM) and input/output (I/O) mapping register (INIT)
is a special-purpose 8-bit register that is used during initialization to change the
default locations of RAM and control registers within the MCU memory map. It can
be written to only once within the first 64 E-clock cycles after a reset in normal
modes. Thereafter, it becomes a read-only register.
RAM2–RAM0 (INIT bits 7–4) specify the starting address for the 192 bytes of static
RAM. REG3–REG0 (INIT bits 3–0) specify the starting address for the control and
status register block. In each case, the four RAM or REG bits become the four
upper bits of the 16-bit address of the RAM or register. Since the INIT register is
set to $00 by reset, the internal registers begin at $0000 and RAM begins at $0040.
Throughout this document, control and status register addresses are displayed
with the high-order digit shown as a bold 0. This convention indicates that the
register block may be relocated to any 4-K memory page, but that its default
location is $0000.
RAM and the control and status registers can be relocated independently. If the
control and status registers are relocated in such a way as to conflict with PROM,
then the register block takes priority, and the EPROM or OTPROM at those
locations becomes inaccessible. No harmful conflicts result. Lower priority
resources simply become inaccessible. Similarly, if an internal resource conflicts
with an external device, no harmful conflict results, since data from the external
device is not applied to the internal data bus. Thus, it cannot interfere with the
internal read.
NOTE:
There are unused register locations in the 64-byte control and status register block.
Reads of these unused registers return data from the undriven internal data bus,
not from another source that happens to be located at the same address.
2.3.3 Configuration Control Register
The configuration control register (CONFIG) controls the presence of OTPROM or
EPROM in the memory map and enables the computer operating properly (COP)
watchdog system.
This register is writable only once in expanded and single-chip modes (SMOD = 0).
In these mode, the COP watchdog timer is enabled out of reset. In all modes,
except normal expanded, EPROM is enabled and located at $F000–$FFFF. In
Address:
$003D
Bit 7
654321
Bit 0
Read:
RAM3
RAM2
RAM1
RAM0
REG3
REG2
REG1
REG0
Write:
Reset:
00000000
Figure 2-3. RAM and I/O Mapping Register (INIT)
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