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參數(shù)資料
| 型號(hào)： | MCC68HC711D3 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, UUC |
| 封裝： | DIE |
| 文件頁(yè)數(shù)： | 111/157頁(yè) |
| 文件大?。?/td> | 2252K |
| 代理商： | MCC68HC711D3 |
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Resets, Interrupts, and Low-Power Modes
Interrupts
MC68HC711D3 — Rev. 2
Data Sheet
MOTOROLA
Resets, Interrupts, and Low-Power Modes
57
4.3.5 Priority Structure
Interrupts obey a fixed hardware priority circuit to resolve simultaneous requests.
However one I bit related interrupt source may be elevated to the highest I bit
priority in the resolution circuit.
Six interrupt sources are not masked by the I bit in the CCR and have these fixed
priority relationships:
1.
Reset
2.
Clock monitor failure
3.
COP failure
4.
Illegal opcode
5.
SWI
6.
XIRQ
SWI is actually an instruction and has highest priority, other than resets, in that
once the SWI opcode is fetched, no other interrupt can be honored until the SWI
vector has been fetched.
Each of the previous sources is an input to the priority resolution circuit. The
highest I bit masked priority input to the resolution circuit is assigned to be
connected to any one of the remaining I bit related interrupt sources. This
assignment is made under the software control of the HPRIO register. To avoid
timing races, the HPRIO register can be written only while the I bit related interrupts
are inhibited (I bit of CCR is logic 1). An interrupt that is assigned to this higher
priority position is still subject to masking by any associated control bits or by the I
bit in the CCR. The interrupt vector address is not affected by assigning a source
to the higher priority position.
to normal processing. Figure 4-4 shows how the CPU begins from a reset, and
how interrupt detection relates to normal opcode fetches. Figure 4-5 is an
expansion of a block in Figure 4-4 and shows how interrupt priority is resolved.
Figure 4-6 is an expansion of the SCI interrupt block of Figure 4-4 and shows the
resolution of interrupt sources within the SCI subsystem.
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