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| 型號(hào)： | MCC68HC711D3 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, UUC |
| 封裝： | DIE |
| 文件頁(yè)數(shù)： | 18/157頁(yè) |
| 文件大小： | 2252K |
| 代理商： | MCC68HC711D3 |
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Programmable Timer
Data Sheet
MC68HC711D3 — Rev. 2
114
Programmable Timer
MOTOROLA
In the event counting mode, the 8-bit counter is clocked to increasing values by an
external pin. The maximum clocking rate for the external event counting mode is
the E clock divided by two. In gated time accumulation mode, a free-running
E-clock
÷ 64 signal drives the 8-bit counter, but only while the external PAI pin is
activated. Refer to Table 8-7. The pulse accumulator counter can be read or
written at any time.
Pulse accumulator control bits are also located within two timer registers, TMSK2
and TFLG2, as described here.
8.7.1 Pulse Accumulator Control Register
Four of the pulse accumulator control register (PACTL) bits control an 8-bit pulse
accumulator system. Another bit enables either the OC5 function or the IC4
function, while two other bits select the rate for the real-time interrupt system.
DDRA7 — Data Direction Control for Port A Bit 7
The pulse accumulator uses port A bit 7 as the PAI input, but the pin can also
be used as general-purpose I/O or as an output compare.
NOTE:
Even when port A bit 7 is configured as an output, the pin still drives the input to
the pulse accumulator.
Refer to Section 5. Input/Output (I/O) Ports for more information.
PAEN — Pulse Accumulator System Enable Bit
0 = Pulse accumulator disabled
1 = Pulse accumulator enabled
PAMOD — Pulse Accumulator Mode Bit
0 = Event counter
1 = Gated time accumulation
Table 8-7. Pulse Accumulator Timing in Gated Mode
Selected
Crystal
Common XTAL Frequencies
4.0 MHz
8.0 MHz
12.0 MHz
CPU Clock
(E)
1.0 MHz
2.0 MHz
3.0 MHz
Cycle Time
(1/E)
1000 ns
500 ns
333 ns
(E/26)
(E/214)
1 count -
overflow -
64.0 s
16.384 ms
32.0 s
8.192 ms
21.33 s
5.461 ms
Address:
$0026
Bit 7
654321
Bit 0
Read:
DDRA7
PAEN
PAMOD
PEDGE
DDRA3
I4/O5
RTR1
RTR0
Write:
Reset:
00000000
Figure 8-20. Pulse Accumulator Control Register (PACTL)
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