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參數(shù)資料
| 型號(hào)： | MCC68HC711D3 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, UUC |
| 封裝： | DIE |
| 文件頁(yè)數(shù)： | 118/157頁(yè) |
| 文件大小： | 2252K |
| 代理商： | MCC68HC711D3 |
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Resets, Interrupts, and Low-Power Modes
Interrupts
MC68HC711D3 — Rev. 2
Data Sheet
MOTOROLA
Resets, Interrupts, and Low-Power Modes
63
4.3.6 Highest Priority I Interrupt and Miscellaneous Register (HPRIO)
Four bits of this register (PSEL3–PSEL0) are used to select one of the I bit related
interrupt sources and to elevate it to the highest I bit masked position of the priority
resolution circuit. In addition, four miscellaneous system control bits are included
in this register.
RBOOT — Read Bootstrap ROM
This bit can be read at any time. It can be written only in special modes
(SMOD = 1). In special bootstrap mode, it is set during reset. Reset clears it in
all other modes.
1 = Bootloader ROM is enabled in the memory map at $BF00–$BFFF.
0 = Bootloader ROM is disabled and is not in the memory map.
SMOD and MDA — Special Mode Select and Mode Select A
and MODB input pins at the rising edge of reset. SMOD may be written only in
special modes. It cannot be written to a 1 after being cleared without an interim
reset. MDA may be written at any time in special modes, but only once in normal
modes. An interpretation of the values of these two bits is shown in Table 4-3.
Address:
$003C
Bit 7
654321
Bit 0
Read:
RBOOT
SMOD
MDA
IRVNE
PSEL3
PSEL2
PSEL1
PSEL0
Write:
Reset:
Note 1
0101
1. The values of the RBOOT, SMOD, IRVNE, and MDA bits at reset depend on the
mode during initialization. Refer to Table 4-3.
Figure 4-7. Highest Priority I-Bit Interrupt
and Miscellaneous Register (HPRIO)
Table 4-3. Hardware Mode Select Summary
Inputs
Mode
Latched at Reset
MODB
MODA
SMOD
MDA
10
Single chip
0
1
Expanded multiplexed
0
1
0
Special bootstrap
1
0
1
Special test
1
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