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參數(shù)資料
| 型號(hào)： | MCC68HC711D3 |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, UUC |
| 封裝： | DIE |
| 文件頁(yè)數(shù)： | 107/157頁(yè) |
| 文件大?。?/td> | 2252K |
| 代理商： | MCC68HC711D3 |
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Resets, Interrupts, and Low-Power Modes
Resets
MC68HC711D3 — Rev. 2
Data Sheet
MOTOROLA
Resets, Interrupts, and Low-Power Modes
53
4.2.4 Clock Monitor Reset
The MCU contains a clock monitor circuit that measures the E-clock frequency. If
the E-clock input rate is above approximately 200 kHz, then the clock monitor does
not generate an MCU reset. If the E-clock signal is lost or its frequency falls below
10 kHz, then an MCU reset can be generated, and the RESET pin is driven low to
reset the external system.
4.2.5 System Configuration Options Register
The system configuration options register (OPTION) is a special-purpose register
with several time-protected bits. OPTION is used during initialization to configure
internal system options.
Bits 5, 4, 2, 1, and 0 can be written only once during the first 64 E-clock cycles after
reset in normal modes (where the HPRIO register bit (SMOD) is cleared). In special
modes (where SMOD = 1), the bits can be written at any time. Bit 3 can be written
at anytime.
Bits 7, 6, and 2 — Not implemented
Always read 0.
IRQE — IRQ Edge/Level Sensitivity Select
This bit can be written only once during the first 64 E-clock cycles after reset in
normal modes.
1 = IRQ is configured to respond only to falling edges.
0 = IRQ is configured for low-level wired-OR operation.
DLY — Stop Mode Exit Turnon Delay
This bit is set during reset and can be written only once during the first 64
E-clock cycles after reset in normal modes. If an external clock source rather
than a crystal is used, the stabilization delay can be inhibited because the clock
source is assumed to be stable.
1 = A stabilization delay of 4064 E-clock cycles is imposed before processing
resumes after a stop mode wakeup.
0 = No stabilization delay is imposed after story recovery.
CME — Clock Monitor Enable
1 = Clock monitor circuit is enabled.
0 = Clock monitor circuit is disabled.
Address:
$0039
Bit 7
654321
Bit 0
Read:
0
IRQE
DLY
CME
0
CR1
CR0
Write:
Reset:
00010000
Figure 4-2. System Configuration Options Register (OPTION)
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