
Programmable Timer
Pulse Accumulator
MC68HC711D3 — Rev. 2
Data Sheet
MOTOROLA
Programmable Timer
115
PEDGE — Pulse Accumulator Edge Control Bit
This bit has different meanings depending on the state of the PAMOD bit, as
DDRA3 — Data Direction Register for Port A Bit 3
I4/O5 — Input Capture 4/Output Compare 5 Bit
RTR1 and RTR0 — RTI Interrupt Rate Select Bits
8.7.2 Pulse Accumulator Count Register
The 8-bit read/write pulse accumulator count register (PACNT) contains the count
of external input events at the PAI input or the accumulated count. The counter is
not affected by reset and can be read or written at any time. Counting is
synchronized to the internal PH2 clock so that incrementing and reading occur
during opposite half cycles.
8.7.3 Pulse Accumulator Status and Interrupt Bits
The pulse accumulator control bits, PAOVI and PAII, PAOVF, and PAIF are located
within timer registers TMSK2 and TFLG2.
PAOVI and PAOVF — Pulse Accumulator Interrupt Enable and Overflow Flag
The PAOVF status bit is set each time the pulse accumulator count rolls over
from $FF to $00. To clear this status bit, write a 1 in the corresponding data bit
position (bit 5) of the TFLG2 register. The PAOVI control bit allows configuring
the pulse accumulator overflow for polled or interrupt-driven operation and does
Table 8-8. Pulse Accumulator Edge Control
PAMOD
PEDGE
Action on Clock
0
PAI falling edge increments the counter.
0
1
PAI rising edge increments the counter.
1
0
A 0 on PAI inhibits counting.
1
A 1 on PAI inhibits counting.
Address:
$0027
Bit 7
654321
Bit 0
Read:
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Write:
Reset:
Unaffected by reset
Figure 8-21. Pulse Accumulator Count Register (PACNT)