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| 型號(hào)： | MCC68HC711D3 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, UUC |
| 封裝： | DIE |
| 文件頁(yè)數(shù)： | 106/157頁(yè) |
| 文件大?。?/td> | 2252K |
| 代理商： | MCC68HC711D3 |
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Resets, Interrupts, and Low-Power Modes
Data Sheet
MC68HC711D3 — Rev. 2
52
Resets, Interrupts, and Low-Power Modes
MOTOROLA
4.2.3 Computer Operating Properly (COP) Reset
The MCU contains a watchdog timer that automatically times out unless it is
serviced within a specific time by a program reset sequence. If the COP watchdog
timer is allowed to timeout, a reset is generated, which drives the RESET pin low
to reset the MCU and the external system.
In the MC68HC711D3, the COP reset function is enabled out of reset in normal
modes. If the user does not want the COP enabled, he must write a 1 to the
NOCOP bit of the configuration control register (CONFIG) after reset. This bit is
writable only once after reset in normal modes (see 2.3.3 Configuration Control
Register for more information). Protected control bits (CR1 and CR0) in the
configuration options register (OPTION) allow the user to select one of the four
COP timeout rates. Table 4-1 shows the relationship between CR1 and CR0 and
the COP timeout period for various system clock frequencies.
The sequence for resetting the watchdog timer is:
1.
Write $55 to the COP reset register (COPRST) to arm the COP timer
clearing mechanism.
2.
Write $AA to the COPRST register to clear the COP timer
Both writes must occur in this sequence prior to the timeout, but any number of
instructions can be executed between the two writes.
Table 4-1. COP Time Out Periods
CR0 CR1
E
÷ 215
Divided
By
XTAL = 223
Time Out
–0/+15.6 ms
XTAL =
8.0 MHz
Time Out
–0/+16.4 ms
XTAL =
4.9152 MHz
Time Out
–0/+26.7 ms
XTAL =
4.0 MHz
Time Out
–0/+32.8 ms
XTAL =
3.6864 MHz
Time Out
–0/+35.6 ms
0
1
15.625 ms
16.384 ms
26.667 ms
32.768 ms
35.556 ms
0
1
4
62.5 ms
65.536 ms
106.67 ms
131.07 ms
142.22 ms
1
0
16
250 ms
262.14 ms
426.67 ms
524.29 ms
568.89 ms
1
64
1 sec
1.049 sec
1.707 sec
2.1 sec
2.276 ms
E =
2.1 MHz
2.0 MHz
1.2288 MHz
1.0 MHz
921.6 kHz
Address:
$003A
Bit 7
654321
Bit 0
Read:
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Write:
Reset:
00000000
Figure 4-1. Arm/Reset COP Timer Circuitry Register (COPRST)
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