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參數(shù)資料
| 型號(hào)： | MCC68HC711D3 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, UUC |
| 封裝： | DIE |
| 文件頁(yè)數(shù)： | 68/157頁(yè) |
| 文件大?。?/td> | 2252K |
| 代理商： | MCC68HC711D3 |
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General Description
Data Sheet
MC68HC711D3 — Rev. 2
18
General Description
MOTOROLA
1.8 E-Clock Output (E)
E is the output connection for the internally generated E clock. The signal from E
is used as a timing reference. The frequency of the E-clock output is one fourth that
of the input frequency at the XTAL and EXTAL pins. The E clock can be turned off
in single-chip mode for greater noise immunity if desired. See 4.3.6 Highest
1.9 Interrupt Request (IRQ)
The IRQ input provides a means of applying asynchronous interrupt requests to the
microcontroller unit (MCU). Either negative edge-sensitive triggering or
level-sensitive triggering is program selectable by using the IRQE bit of the
OPTION register. IRQ is always configured to level-sensitive triggering at reset.
While the programmable read-only memory (PROM) is being programmed, this pin
provides the chip enable (CE) signal. To prevent accidental programming of the
PROM during reset, an external resistor is required on IRQ to pull the pin to VDD.
1.10 Non-Maskable Interrupt/Programming Voltage (XIRQ/VPP)
The XIRQ input provides the capability for asynchronously applying non-maskable
interrupts to the MCU after a power-on reset (POR). During reset, the X bit in the
condition code register (CCR) is set masking any interrupt until enabled by
software. This level-sensitive input requires an external pullup resistor to VDD.
In the programming configuration of the bootstrap mode, this pin is used to supply
one-time programmable read-only memory (OTPROM) programming voltage, VPP,
to the MCU. To avoid programming accidents during reset, this pin should be equal
to VDD during normal operation unless XIRQ is active.
1.11 MODA and MODB (MODA/LIR and MODB/VSTBY)
As reset transitions, these pins are used to latch the part into one of the four central
processor unit (CPU) controlled modes of operation. The LIR output can be used
as an aid to debugging once reset is completed. The open-drain LIR pin goes to an
active low during the first E-clock cycle of each instruction and remains low for the
duration of that cycle. The VSTBY input is used to retain random-access memory
(RAM) contents during power down.
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