參數(shù)資料
型號: MCC68HC711D3
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, UUC
封裝: DIE
文件頁數(shù): 134/157頁
文件大?。?/td> 2252K
代理商: MCC68HC711D3
Serial Communications Interface (SCI)
Data Sheet
MC68HC711D3 — Rev. 2
78
Serial Communications Interface (SCI)
MOTOROLA
6.7 SCI Registers
This subsection describes the five addressable registers in the SCI.
6.7.1 SCI Data Register
The SCI data register (SCDR) is a parallel register that performs two functions. It
is the receive data register when it is read, and the transmit data register when it is
written. Reads access the receive data buffer and writes access the transmit data
buffer. Receive and transmit are double buffered.
6.7.2 SCI Control Register 1
The SCI control register 1 (SCCR1) provides the control bits that determine word
length and select the method used for the wakeup feature.
R8 — Receive Data Bit 8
If M bit is set, R8 stores the ninth bit in the receive data character.
T8 — Transmit Data Bit 8
If M bit is set, T8 stores ninth bit in transmit data character.
M — Mode Bit
The mode bit selects character format
0 = Start bit, 8 data bits, 1 stop bit
1 = Start bit, 9 data bits, 1 stop bit
WAKE — Wakeup by Address Mark/Idle Bit
0 = Wakeup by IDLE line recognition
1 = Wakeup by address mark (most significant data bit set)
Address:
$002F
Bit 7
654321
Bit 0
Read:
R7/T7
R6/T6
R5/T5
R4/T4
R3/T3
R2/T2
R1/T1
R0/T0
Write:
Reset:
Unaffected by reset
Figure 6-3. SCI Data Register (SCDR)
Address:
$002C
Bit 7
654321
Bit 0
Read:
R8
T8
0
M
WAKE
0
Write:
Reset:
U
000000
U = Unaffected
Figure 6-4. SCI Control Register 1 (SCCR1)
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