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| 型號： | MC92603VF |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 53/126頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX ETH QUAD GIG 256-MAPBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 4/4 |
| 規(guī)程： | 千兆位以太網(wǎng) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-LBGA |
| 供應(yīng)商設(shè)備封裝： | 256-MAPBGA |
| 包裝： | 托盤 |
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Transmitter
MC92603 Quad Gigabit Ethernet Transceiver Reference Manual, Rev. 1
2-10
Freescale Semiconductor
When an auto-negotiate sequence is started, the transmitter initially sends at least 10 milliseconds of
/C1/C2/ sequences with all zeros as the Configuration Register contents. This forces the remote device to
also enter auto-negotiate mode.
The contents of the configuration register are continuously sent until the associated receiver detects the
compatible configuration being sent from the link partner. The MC92603 is configured as full-duplex
1-Gigabit; therefore, the configuration is as shown in Figure 2-2. For register details, see Section 4.2.4,
The ‘Ack’ bit is asserted when three consecutive matching configuration register values are received. The
auto-negotiate state is complete when three consecutive matching configuration register values are
received with the ‘Ack’ bit set. The transmitter continues sending auto-negotiate sequences once the
auto-negotiate sequence is complete for at least 10 ms.
NOTE
See the state diagram in Figure 37-6 of the IEEE Std. 802.3-2002
specification [4] for a complete description.
2.5.1.2
Ethernet Data Transmission Process
Transmitter operation is controlled by the two input control signals XMIT_x_ENABLE and
XMIT_x_ERR. See Table 3-9 for the complete GMII interface to the MC92603.
When both XMIT_x_ENABLE and XMIT_x_ERR inputs are low, the transmitter broadcasts IDLE
Ordered_sets. Whenever a new series of IDLE Ordered_sets are started, the first IDLE Ordered_set may
be an I1 Ordered_set to correct the running disparity, all subsequent IDLE Ordered sets will be I2s. The
transmitter must be aware of even/oddness. K28.5 code groups are transmitted as the ‘even’ code group
and either D5.6 or D16.2 as the ‘odd’ code group. This even/odd flag is set at initialization and must be
maintained since other events will depend on this even/oddness.
When XMIT_x_ENABLE is raised, the data on the XMIT_x_7 through XMIT_x_0 inputs is assumed to
be the first byte of an 8-byte preamble. The preamble usually consists of 7 consecutive 0x55 code groups
followed by a 0xD5 code group. The transmitter replaces the first 0x55 code group in the preamble with a
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Function Next
Page1
Ack2 RF23 RF1 3
Reserved
PS24 PS14 HD5
FD6
Reserved
Value
0
1/0
0
1
0
1 Next Page—MC92603 does not support multiple pages of configuration registers.
2 Ack—Asserted when the receiver detects a valid configuration from the other transmitter.
3 RF1 and RF2— ‘Remote faults’ as detected by the receiver.
4 PS1 and PS2—Pause control bits that reflect the values of MDIO register 4’s bits 12 and 13, respectively. This register
may be modified via the MDIO interface.
5 HD—MC92603 does not support half-duplex mode.
6 FD—MC92603 always runs in full-duplex mode.
Figure 2-2. Configuration Register
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