參數(shù)資料
型號(hào)： MC92603VF
廠商： Freescale Semiconductor
文件頁數(shù)： 114/126頁
文件大小： 0K
描述： IC TXRX ETH QUAD GIG 256-MAPBGA
標(biāo)準(zhǔn)包裝： 1
類型： 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù)： 4/4
規(guī)程： 千兆位以太網(wǎng)
電源電壓： 4.5 V ~ 5.5 V
安裝類型： 表面貼裝
封裝/外殼： 256-LBGA
供應(yīng)商設(shè)備封裝： 256-MAPBGA
包裝： 托盤
Electrical Specifications and Characteristics
MC92603 Quad Gigabit Ethernet Transceiver Reference Manual, Rev. 1
7-6
Freescale Semiconductor
7.3.2
Receiver Interface Timing
The data output timing at the receiver interface may be single data rate (non-DDR) or double data rate
(DDR) as described in Section 3.4, “Receiver Interface Configuration.” Additionally, the valid data is
sourced simultaneously with, or centered on, the RECV_x_CLK output, depending on the state of the
control signal, RECV_CLK_CENT.
When the control signal RECV_CLK_CENT = high, the data is centered about the receiver clock edge.
When RECV_CLK_CENT = low, the receiver clock edge is aligned (co-incident) with the data. See
Section 3.6, “Receiver Interface Timing Modes,” for more on receiver interface timing.
Table 7-6 shows the receiver clock cycle time and the target or typical offset of the clock edge with respect
to the data depending on the device application configuration. Note that the complement of the receiver
clock, RECV_x_RCLK_B, is only valid and available in TBI and RTBI Ethernet compliant applications
modes.
Table 7-6 also lists references to timing figures in the following receiver interface timing sections.
Table 7-6. Target Receiver Clock Offset Relative to Data
Application
Mode
DDR
TBIE and
COMPAT =
High
HSE
Receiver
Clock Cycle
Time1
(ns)
1 Assumes 125-MHz reference clock if HSE is disabled and 62.5-MHz reference clock if HSE is enabled.
RECV_x_
RCLK
RECV_x_
RCLK_B
Clock Offset
to Data
(ns)
Reference
Figure No.
GMII or 8-/10-bit
backplane
Low
False
Low
8
Valid
Low
4
Low
False
High
16
Valid
Low
8
Ethernet TBI
Low
True
Low
16
Valid
4
Low
True
High
32
Valid
8
RGMII or 4-/5-bit
backplane
High
False
Low
8
Valid
Low
2
High
False
High
16
Valid
Low
4
Ethernet RTBI
High
True
Low
8
Valid
2
High
True
High
16
Valid
4
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