參數(shù)資料
型號(hào): MC92603VF
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 51/126頁(yè)
文件大?。?/td> 0K
描述: IC TXRX ETH QUAD GIG 256-MAPBGA
標(biāo)準(zhǔn)包裝: 1
類(lèi)型: 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù): 4/4
規(guī)程: 千兆位以太網(wǎng)
電源電壓: 4.5 V ~ 5.5 V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 256-LBGA
供應(yīng)商設(shè)備封裝: 256-MAPBGA
包裝: 托盤(pán)
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Transmitter
MC92603 Quad Gigabit Ethernet Transceiver Reference Manual, Rev. 1
2-8
Freescale Semiconductor
When using the MC92603 in the backplane applications (COMPAT = low), it is not necessary to use the
8B/10B code set. However, special care must be taken. The data must exhibit the same properties as
8B/10B coded data. DC balance must be maintained and there must be sufficient transition density to
ensure reliable clock and data recovery at the receiver. If running in the Ethernet TBI or RTBI mode, the
data will be 8B/10B data.
NOTE
If the code used is not 8B/10B, then it must support the K28.5 IDLE code
(this only applies to backplane mode; Ethernet-TBI mode is assumed to use
8B/10B). The code must be such to guarantee that no two codes, when
concatenated, produce the 8-bit COMMA pattern as defined above.
The receivers require that COMMA code groups (K28.1, K28.5, or K28.7) be transmitted for byte
synchronization. The 8-bit pattern (‘00111110xx’ or ‘11000001xx,’ ordered from bits 0–7) is used for
alignment and link-to-link synchronization when operating in any of the byte or word synchronization
modes. The pattern of code groups and data required to achieve word synchronization (available only in
backplane application mode, COMPAT = low) depends on the configuration of the receiver. The
appropriate sequence must be applied through the 10-/5-bit interface.
Transmitting coded data with the reduced interface mode is shown in Table 2-6. The transmitter functional
operation is the same as discussed above, except the data is entered on both edges of the transmitter input
clock, XMIT_x_CLK.
The 10 bits of uncoded data are entered with the least significant 5 bits on the rising clock and the most
significant bits on the falling clock edge.
Table 2-6. Transmitter Inputs for RTBI Operating Mode
Data on Rising Edge of
XMIT_x_CLK
Data on Falling Edge of
XMIT_x_CLK
MC92603 Signal Name
Data bit 4
Data bit 9
XMIT_x_ENABLE
Data bits 3–0
Data bits 8–5
XMIT_x_3/XMIT_x_0
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