參數(shù)資料
型號: MC92603VF
廠商: Freescale Semiconductor
文件頁數(shù): 17/126頁
文件大?。?/td> 0K
描述: IC TXRX ETH QUAD GIG 256-MAPBGA
標(biāo)準(zhǔn)包裝: 1
類型: 收發(fā)器
驅(qū)動器/接收器數(shù): 4/4
規(guī)程: 千兆位以太網(wǎng)
電源電壓: 4.5 V ~ 5.5 V
安裝類型: 表面貼裝
封裝/外殼: 256-LBGA
供應(yīng)商設(shè)備封裝: 256-MAPBGA
包裝: 托盤
8B/10B Coding Scheme
MC92603 Quad Gigabit Ethernet Transceiver Reference Manual, Rev. 1
Freescale Semiconductor
B-3
B.1.3
Calculating Running Disparity
Running disparity improves error detection and recovery. The rules for calculating the running disparity
for sub-blocks are as follows (reference Fibre Channel, Gigabit Communications and I/O for Computer
Networks):
Running disparity at the end of any sub-block is positive if (1) the encoded sub-block contains
more 1s than 0s, (2) if the 6-bit sub-block is 6’b00 0111, or (3) if the 4-bit sub-block is 4’b0011.
Running disparity at the end of any sub-block is negative if (1) the encoded sub-block contains
more 0 than 1 bits, (2) if the 6-bit sub-block is 6’b11 1000, or (3) if the 4-bit sub-block is 4’b1100.
Otherwise, running disparity at the end of the sub-block is the same as at the beginning of the
sub-block.
B.2
Data Tables
Table B-2 displays the full valid data character 8B/10B codes. The values in the ‘Data Value HGFEDCBA’
column are the possible bit values of the unencoded transmission characters. The current RD values are
the possible positive and negative running disparity values.
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