Design Platform (BR1570) describes the technical " />
參數(shù)資料
型號(hào): MC92603VF
廠商: Freescale Semiconductor
文件頁數(shù): 34/126頁
文件大?。?/td> 0K
描述: IC TXRX ETH QUAD GIG 256-MAPBGA
標(biāo)準(zhǔn)包裝: 1
類型: 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù): 4/4
規(guī)程: 千兆位以太網(wǎng)
電源電壓: 4.5 V ~ 5.5 V
安裝類型: 表面貼裝
封裝/外殼: 256-LBGA
供應(yīng)商設(shè)備封裝: 256-MAPBGA
包裝: 托盤
MC92603 Quad Gigabit Ethernet Transceiver Reference Manual, Rev. 1
Freescale Semiconductor
xv
Design Platform (BR1570) describes the technical design process used in developing a high-speed
backplane reference design.
Additional literature is published as new processors become available. For a current list of
documentation, refer to http://www.freescale.com.
Conventions
This document uses the following notational conventions:
Book titles in text are set in italics
Internal signals are set in italics, for example, loopback_data
*
Notation for multiplication
0x
Prefix to denote hexadecimal number
0b
Prefix to denote binary number
x
In some contexts, such as signal encodings, an un-italicized x indicates a don’t care.
x
An italicized x indicates an alphanumeric variable.
n
An italicized n indicates a numeric variable.
Signals
A bar over a signal name indicates that the signal is active low—for example, RESET and TRST. Active
low signals are referred to as asserted (active) when they are low and negated when they are high. Signals
that are not active low, such as XMIT_A_ENABLE and DROP_SYNC, are referred to as asserted when
they are high and negated when they are low.
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