參數(shù)資料
型號: MC92603VF
廠商: Freescale Semiconductor
文件頁數(shù): 102/126頁
文件大?。?/td> 0K
描述: IC TXRX ETH QUAD GIG 256-MAPBGA
標(biāo)準(zhǔn)包裝: 1
類型: 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù): 4/4
規(guī)程: 千兆位以太網(wǎng)
電源電壓: 4.5 V ~ 5.5 V
安裝類型: 表面貼裝
封裝/外殼: 256-LBGA
供應(yīng)商設(shè)備封裝: 256-MAPBGA
包裝: 托盤
MC92603 Quad Gigabit Ethernet Transceiver Reference Manual, Rev. 1
Freescale Semiconductor
6-1
Chapter 6
Test Features
This chapter consists of the following sections:
The MC92603 supports several test modes for built-in system test, BIST, and production testing. The
MC92603 also has an IEEE Std. 1149.1 [3] compliant test access port and boundary scan architecture
implementations. This chapter covers the JTAG implementation and the system accessible test modes.
6.1
IEEE Std. 1149.1 Implementation
This section describes the IEEE Std. 1149.1 compliant test access port and boundary scan architecture
implementation in the MC92603.
6.1.1
Test Access Port (TAP) Interface Signals
Table 6-1 lists the interface signals for the TAP.
NOTE
The TMS, TDI, and TRST, have 100-K
pull-ups. If TRST is not held low
during power up or does not receive an active low preset after power up, the
test logic may assume an indeterminate state disabling some of the normal
transceiver functions. It is recommended that TRST be terminated in one of
the following ways:
Drive TRST with a TAP controller that provides a reset after power up.
Connect TRST to RESET.
Terminate TRST with a 1-KW resistor (or hardwire) to ground.
Table 6-1. TAP Interface Signals
Signal
Name
Description
Function
Direction
Active
State
TCK
Test clock
Test logic clock
Input
TMS
Test mode select
TAP mode control input
Input
TDI
Test data in
Serial test instruction/data input
Input
TRST
Test reset bar
Asynchronous test controller reset
Input
Low
TDO
Test data out
Serial test instruction/data output
Output
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