參數(shù)資料
型號: MC92603VF
廠商: Freescale Semiconductor
文件頁數(shù): 121/126頁
文件大小: 0K
描述: IC TXRX ETH QUAD GIG 256-MAPBGA
標(biāo)準(zhǔn)包裝: 1
類型: 收發(fā)器
驅(qū)動器/接收器數(shù): 4/4
規(guī)程: 千兆位以太網(wǎng)
電源電壓: 4.5 V ~ 5.5 V
安裝類型: 表面貼裝
封裝/外殼: 256-LBGA
供應(yīng)商設(shè)備封裝: 256-MAPBGA
包裝: 托盤
Electrical Specifications and Characteristics
MC92603 Quad Gigabit Ethernet Transceiver Reference Manual, Rev. 1
7-12
Freescale Semiconductor
7.3.4
Serial Data Link Timing
The following section provides the serial data link timing for the MC92603. Figure 7-8 provides the link
differential output timing diagram.
Figure 7-8. Link Differential Output Timing Diagram
Table 7-12 provides the link differential output timing specifications.
Figure 7-9 provides the link differential input timing diagram.
Figure 7-9. Link Differential Input Timing Diagram
Table 7-13 provides the link differential input timing specifications.
Table 7-12. Link Differential Output Specifications
Symbol
Characteristic
Min
Max
Unit
Tj
Total jitter 1
1 Measured between 50–50 percent points.
0.24
UI
Tdj
Deterministic jitter 1
0.12
UI
Tds
Differential skew 1
25
ps
Xla
Transmit latency 2
2 Rising edge XMIT_x_CLK to bit 0 transmit.
57
bit-times
Table 7-13. Link Differential Input Timing Specifications
Symbol
Characteristic
Min
Max
Unit
Tr
Link input rise time1
1 Measured between 10–90 percent points.
300
ps
Tf
Link input fall time 1
300
ps
Tjtol
Total jitter tolerance 2,3
2 Measured between 50–50 percent points, 125 MHz REF_CLK, 1.25 Gbaud.
3 Per IEEE Std 802.3 specification [4].
0.71
UI
Tdjtol
Deterministic jitter tolerance 2, 3
0.45
UI
Tdstol
Differential skew tolerance 2, 3
175
ps
Rlat
Receive latency4
4 Bit 0 at receiver input to parallel data out (RCCE = high, WSYNC1 and WSYNC0 = low).
127
bit-times
Tacq
Receiver phase acquisition time
TBD 5
5 Measured with worst-case eye opening, Idle pattern, and reference PLL locked.
bit-times
Tj
Tds
XLINK_x_N
XLINK_x_P
Tdstol
RLINK_x_N
RLINK_x_P
Tjtol
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