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參數(shù)資料
| 型號(hào)： | MC68330FC16 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 16.78 MHz, MICROPROCESSOR, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁(yè)數(shù)： | 99/261頁(yè) |
| 文件大?。?/td> | 1153K |
| 代理商： | MC68330FC16 |
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5- 84
MC68330 USER'S MANUAL
MOTOROLA
5.7.2.1 ENABLING BDM. Accidentally entering BDM in a nondevelopment environment
could lock up the CPU32 since the serial command interface would probably not be
available. For this reason, BDM is enabled during reset via the breakpoint (
BKPT) signal.
BDM operation is enabled when
BKPT is asserted (low) at the rising edge of RESET. BDM
remains enabled until the next system reset. A high
BKPT signal on the trailing edge of
RESET disables BDM. BKPT is relatched on each rising transition of RESET. BKPT is
synchronized internally and must be held low for at least two clock cycles prior to negation
of
RESET.
BDM enable logic must be designed with special care. If hold time on
BKPT (after the
trailing edge of
RESET) extends into the first bus cycle following reset, this bus cycle could
be tagged with a breakpoint. Refer to Section 3 Bus Operation for timing information.
5.7.2.2 BDM SOURCES. When BDM is enabled, any of several sources can cause the
transition from normal mode to BDM. These sources include external breakpoint
hardware, the BGND instruction, a double bus fault, and internal peripheral breakpoints. If
BDM is not enabled when an exception condition occurs, the exception is processed
normally. Table 5-21 summarizes the processing of each source for both enabled and
disabled cases. As depicted in the table, the BKPT instruction never causes a transition
into BDM.
Table 5-21. BDM Source Summary
Source
BDM Enabled
BDM Disabled
BKPT
Background
Breakpoint Exception
Double Bus Fault
Background
Halted
BGND Instruction
Background
Illegal Instruction
BKPT Instruction
Opcode Substitution/
Illegal Instruction
Opcode Substitution/
Illegal Instruction
5.7.2.2.1 External
BKPT Signal. Once enabled, BDM is initiated whenever assertion of
BKPT is acknowledged. If BDM is disabled, a breakpoint exception (vector $0C) is
acknowledged. The
BKPT input has the same timing relationship to the data strobe trailing
edge as does read cycle data. There is no breakpoint acknowledge bus cycle when BDM
is entered.
5.7.2.2.2 BGND Instruction. An illegal instruction, $4AFA, is reserved for use by
development tools. The CPU32 defines $4AFA (BGND) to be a BDM entry point when
BDM is enabled. If BDM is disabled, an illegal instruction trap is acknowledged. Illegal
instruction traps are discussed in 5.6.2.8 Illegal or Unimplemented Instructions.
5.7.2.2.3 Double Bus Fault. The CPU32 normally treats a double bus fault (two bus faults
in succession) as a catastrophic system error and halts. When this condition occurs during
initial system debug (a fault in the reset logic), further debugging is impossible until the
problem is corrected. In BDM, the fault can be temporarily bypassed so that its origin can
be isolated and eliminated.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68332AMPV16 | 32-BIT, 16.78 MHz, MICROCONTROLLER, PQFP144 |
| MC68332GMPV20 | 32-BIT, 20.97 MHz, MICROCONTROLLER, PQFP144 |
| MC68332AVPV16 | 32-BIT, 16.78 MHz, MICROCONTROLLER, PQFP144 |
| MC68332GMPV16 | 32-BIT, 16.78 MHz, MICROCONTROLLER, PQFP144 |
| SPAKMC332GMPV20 | 32-BIT, 20.97 MHz, MICROCONTROLLER, PQFP144 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68330FE16 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated CPU32 Processor |
| MC68330FE16V | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated CPU32 Processor |
| MC68330FE25 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated CPU32 Processor |
| MC68330FE8V | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated CPU32 Processor |
| MC68330FG16 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated CPU32 Processor |
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