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參數(shù)資料
| 型號(hào)： | MC68330FC16 |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 16.78 MHz, MICROPROCESSOR, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁(yè)數(shù)： | 199/261頁(yè) |
| 文件大?。?/td> | 1153K |
| 代理商： | MC68330FC16 |
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3- 14
MC68330 USER’S MANUAL
MOTOROLA
3.2.4 Bus Operation
The MC68330 bus is asynchronous, allowing external devices connected to the bus to
operate at clock frequencies different from the clock for the MC68330. Bus operation uses
the handshake lines (
AS, DS, DSACK1, DSACK0, BERR, and HALT) to control data
transfers.
AS signals a valid address on the address bus, and DS is used as a condition
for valid data on a write cycle. Decoding the size outputs and lower address line A0
provides strobes that select the active portion of the data bus. The slave device (memory
or peripheral) responds by placing the requested data on the correct portion of the data
bus for a read cycle or by latching the data on a write cycle; the slave asserts the
DSACK1/DSACK0 combination that corresponds to the port size to terminate the cycle.
Alternatively, the SIM40 can be programmed to assert the
DSACK1/DSACK0
combination internally and respond for the slave. If no slave responds or the access is
invalid, external control logic may assert
BERR, or BERR with HALT to abort or retry the
bus cycle, respectively.
DSACKx can be asserted before the data from a slave device is
valid on a read cycle. The length of time that
DSACKx may precede data must not exceed
a specified value in any asynchronous system to ensure that valid data is latched into the
MC68330. (See MC68330/D,
MC68330 Technical Summary for timing parameters.) Note
that no maximum time is specified from the assertion of
AS to the assertion of DSACKx.
Although the MC68330 can transfer data in a minimum of three clock cycles when the
cycle is terminated with
DSACKx, the MC68330 inserts wait cycles in clock-period
increments until
DSACKx is recognized. BERR and/or HALT can be asserted after
DSACKx is asserted. BERR and/or HALT must be asserted within the time specified after
DSACKx is asserted in any asynchronous system. If this maximum delay time is violated,
the MC68330 may exhibit erratic behavior.
3.2.5 Synchronous Operation with
DSACKx
Although cycles terminated with
DSACKx are classified as asynchronous, cycles
terminated with
DSACKx can also operate synchronously in that signals are interpreted
relative to clock edges. The devices that use these cycles must synchronize the response
to the MC68330 clock (CLKOUT) to be synchronous. Since the devices terminate bus
cycles with
DSACKx, the dynamic bus sizing capabilities of the MC68330 are available.
The minimum cycle time for these cycles is also three clocks. To support systems that use
the system clock to generate
DSACKx and other asynchronous inputs, the asynchronous
input setup time and the asynchronous input hold time are given. If the setup and hold
times are met for the assertion or negation of a signal, such as
DSACKx, the MC68330 is
guaranteed to recognize that signal level on that specific falling edge of the system clock.
If the assertion of
DSACKx is recognized on a particular falling edge of the clock, valid
data is latched into the MC68330 (for a read cycle) on the next falling clock edge if the
data meets the data setup time. In this case, the parameter for asynchronous operation
can be ignored. The timing parameters are described in MC68330/D,
MC68330 Technical
Summary.
If a system asserts
DSACKx for the required window around the falling edge of S2 and
obeys the proper bus protocol by maintaining
DSACKx (and/or BERR/HALT) until and
throughout the clock edge that negates
AS (with the appropriate asynchronous input hold
time), no wait states are inserted. The bus cycle runs at its maximum speed for bus cycles
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| MC68332AMPV16 | 32-BIT, 16.78 MHz, MICROCONTROLLER, PQFP144 |
| MC68332GMPV20 | 32-BIT, 20.97 MHz, MICROCONTROLLER, PQFP144 |
| MC68332AVPV16 | 32-BIT, 16.78 MHz, MICROCONTROLLER, PQFP144 |
| MC68332GMPV16 | 32-BIT, 16.78 MHz, MICROCONTROLLER, PQFP144 |
| SPAKMC332GMPV20 | 32-BIT, 20.97 MHz, MICROCONTROLLER, PQFP144 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MC68330FE16 | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:Integrated CPU32 Processor |
| MC68330FE16V | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:Integrated CPU32 Processor |
| MC68330FE25 | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:Integrated CPU32 Processor |
| MC68330FE8V | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:Integrated CPU32 Processor |
| MC68330FG16 | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:Integrated CPU32 Processor |
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