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參數(shù)資料
| 型號(hào)： | MC68330FC16 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 16.78 MHz, MICROPROCESSOR, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁數(shù)： | 225/261頁 |
| 文件大?。?/td> | 1153K |
| 代理商： | MC68330FC16 |
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3- 38
MC68330 USER’S MANUAL
MOTOROLA
When a double bus fault occurs, the MC68330 halts and drives the
HALT line low. Only a
reset operation can restart a halted MC68330. However, bus arbitration can still occur
(refer to 3.6 Bus Arbitration). A second bus error or address error that occurs after
exception processing has completed (during the execution of the exception handler
routine, or later) does not cause a double bus fault. A bus cycle that is retried does not
constitute a bus error or contribute to a double bus fault. The MC68330 continues to retry
the same bus cycle as long as the external hardware requests it.
Reset can also be generated internally by the halt monitor (see Section 5 CPU32).
3.6 BUS ARBITRATION
The bus design of the MC68330 provides for a single bus master at any one time, either
the MC68330 or an external device. One or more of the external devices on the bus can
have the capability of becoming bus master for the external bus, but not the MC68330
internal bus. Bus arbitration is the protocol by which an external device becomes bus
master; the bus controller in the MC68330 manages the bus arbitration signals so that the
MC68330 has the lowest priority. External devices that need to obtain the bus must assert
the bus arbitration signals in the sequences described in the following paragraphs.
Systems that include several devices that can become bus master require external
circuitry to assign priorities to the devices, so that when two or more external devices
attempt to become bus master at the same time, the one having the highest priority
becomes bus master first. The sequence of the protocol is as follows:
1. An external device asserts
BR.
2. The MC68330 asserts
BG to indicate that the bus is available.
3. The external device asserts
BGACK to indicate that it has assumed bus mastership.
BR may be issued any time during a bus cycle or between cycles. BG is asserted in
response to
BR. To guarantee operand coherency, BG is only asserted at the end of an
operand transfer. Additionally,
BG is not asserted until the end of a read-modify-write
operation (when
RMC is negated) in response to a BR signal. When the requesting device
receives
BG and more than one external device can be bus master, the requesting device
should begin whatever arbitration is required. When it assumes bus mastership, the
external device asserts
BGACK and maintains BGACK during the entire bus cycle (or
cycles) for which it is bus master. The following conditions must be met for an external
device to assume mastership of the bus through the normal bus arbitration procedure: 1) It
must have received
BG through the arbitration process, and 2) BGACK must be inactive,
indicating that no other bus master has claimed ownership of the bus.
Figure 3-22 is a flowchart showing the detail involved in bus arbitration for a single device.
This technique allows processing of bus requests during data transfer cycles. Refer to
Figures 3-23 and 3-24 for the bus arbitration timing diagram.
BR is negated at the time that BGACK is asserted. This type of operation applies to a
system consisting of the MC68330 and one device capable of bus mastership. In a system
having a number of devices capable of bus mastership,
BR from each device can be wire-
ORed to the MC68330. In such a system, more than one bus request could be asserted
simultaneously.
BG is negated a few clock cycles after the transition of BGACK. However,
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