
MOTOROLA
MC68330 USER’S MANUAL
ix
TABLE OF CONTENTS (Continued)
Paragraph
Page
Number
Title
Number
5.6.2.12
Return from Exception................................................................................... 5-72
5.6.3
Fault Recovery................................................................................................ 5-72
5.6.3.1
Types of Faults ............................................................................................... 5-75
5.6.3.1.1
Type I: Released Write Faults...................................................................... 5-75
5.6.3.1.2
Type II: Prefetch, Operand, RMW, and MOVEP Faults............................ 5-75
5.6.3.1.3
Type III: Faults during MOVEM Operand Transfer ................................... 5-76
5.6.3.1.4
Type IV: Faults during Exception Processing........................................... 5-77
5.6.3.2
Correcting a Fault .......................................................................................... 5-77
5.6.3.2.1
Type I — Completing Released Writes via Software .............................. 5-77
5.6.3.2.2
Type I — Completing Released Writes via RTE....................................... 5-78
5.6.3.2.3
Type II — Correcting Faults via RTE........................................................... 5-78
5.6.3.2.4
Type III — Correcting Faults via Software ................................................. 5-78
5.6.3.2.5
Type III — Correcting Faults by Conversion and Restart........................ 5-79
5.6.3.2.6
Type III — Correcting Faults via RTE.......................................................... 5-79
5.6.3.2.7
Type IV — Correcting Faults via Software ................................................ 5-80
5.6.4
CPU32 Stack Frames ................................................................................... 5-80
5.6.4.1
Four-Word Stack Frame ............................................................................... 5-80
5.6.4.2
Six-Word Stack Frame.................................................................................. 5-81
5.6.4.3
BERR Stack Frame ........................................................................................ 5-81
5.7
Development Support................................................................................... 5-84
5.7.1
CPU32 Integrated Development Support................................................. 5-84
5.7.1.1
Background Debug Mode (BDM) Overview ............................................. 5-84
5.7.1.2
Deterministic Opcode Tracking Overview................................................. 5-85
5.7.1.3
On-Chip Hardware Breakpoint Overview.................................................. 5-85
5.7.2
Background Debug Mode (BDM) ............................................................... 5-85
5.7.2.1
Enabling BDM ................................................................................................ 5-86
5.7.2.2
BDM Sources ................................................................................................. 5-87
5.7.2.2.1
External BKPT Signal ................................................................................... 5-87
5.7.2.2.2
BGND Instruction ........................................................................................... 5-87
5.7.2.2.3
Double Bus Fault ........................................................................................... 5-87
5.7.2.3
Entering BDM ................................................................................................. 5-87
5.7.2.4
Command Execution..................................................................................... 5-88
5.7.2.5
Background Mode Registers ....................................................................... 5-88
5.7.2.5.1
Fault Address Register (FAR) ...................................................................... 5-88
5.7.2.5.2
Return Program Counter (RPC) .................................................................. 5-88
5.7.2.5.3
Current Instruction Program Counter (PCC)............................................. 5-88
5.7.2.6
Returning from BDM...................................................................................... 5-89
5.7.2.7
Serial Interface............................................................................................... 5-89
5.7.2.7.1
CPU32 Serial Logic ...................................................................................... 5-90
5.7.2.7.2
Development System Serial Logic............................................................. 5-92
5.7.2.8
Command Set ................................................................................................ 5-94
5.7.2.8.1
Command Format.......................................................................................... 5-94
5.7.2.8.2
Command Sequence Diagrams................................................................. 5-95
5.7.2.8.3
Command Set Summary.............................................................................. 5-96
5.7.2.8.4
Read A/D Register (RAREG/RDREG)......................................................... 5-97
5.7.2.8.5
Write A/D Register (WAREG/WDREG) ....................................................... 5-98