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MC68330 USER’S MANUAL
MOTOROLA
TABLE OF CONTENTS (Continued)
Paragraph
Page
Number
Title
Number
4.2.3.3
Clock Control.................................................................................................. 4-12
4.2.4
Chip-Select Function .................................................................................... 4-12
4.2.4.1
Programmable Features............................................................................... 4-13
4.2.4.2
Global Chip-Select Operation..................................................................... 4-13
4.2.5
External Bus Interface................................................................................... 4-14
4.2.5.1
Port A................................................................................................................ 4-14
4.2.5.2
Port B................................................................................................................ 4-14
4.2.6
Low-Power Stop ............................................................................................ 4-15
4.2.7
Freeze.............................................................................................................. 4-15
4.3
Programmer's Model..................................................................................... 4-16
4.3.1
Module Base Address Register................................................................... 4-17
4.3.2
System Configuration and Protection Registers...................................... 4-18
4.3.2.1
Module Configuration Register (MCR)....................................................... 4-18
4.3.2.2
Autovector Register (AVR)............................................................................ 4-20
4.3.2.3
Reset Status Register (RSR)........................................................................ 4-20
4.3.2.4
Software Interrupt Vector Register (SWIV)................................................ 4-21
4.3.2.5
System Protection Control Register (SYPCR).......................................... 4-21
4.3.2.6
Periodic Interrupt Control Register (PICR) ................................................ 4-23
4.3.2.7
Periodic Interrupt Timer Register (PITR).................................................... 4-24
4.3.2.8
Software Service Register (SWSR) ........................................................... 4-24
4.3.3
Clock Synthesizer Control Register (SYNCR) ......................................... 4-25
4.3.4.
Chip-Select Registers ................................................................................... 4-26
4.3.4.1
Base Address Registers ............................................................................... 4-26
4.3.4.2
Address Mask Registers ............................................................................... 4-27
4.3.4.3
Chip-Select Registers Programming Example ........................................ 4-29
4.3.5
External Bus Interface Control..................................................................... 4-29
4.3.5.1
Port A Pin Assignment Register 1 (PPARA1)............................................ 4-29
4.3.5.2
Port A Pin Assignment Register 2 (PPARA2)............................................ 4-30
4.3.5.3
Port A Data Direction Register (DDRA)...................................................... 4-30
4.3.5.4
Port A Data Register (PORTA)..................................................................... 4-30
4.3.5.5
Port B Pin Assignment Register (PPARB) ................................................. 4-31
4.3.5.6
Port B Data Direction Register (DDRB)...................................................... 4-31
4.3.5.7
Port B Data Register (PORTB, PORTB1) ................................................... 4-31
Section 5
CPU32
5.1
Overview.............................................................................................................5-1
5.1.1
Features..............................................................................................................5-2
5.1.2
Virtual Memory ..................................................................................................5-2
5.1.3
Loop Mode Instruction Execution ..................................................................5-3
5.1.4
Vector Base Register........................................................................................5-4
5.1.5
Exception Handling..........................................................................................5-4
5.1.6
Addressing Modes............................................................................................5-5
5.1.7
Instruction Set....................................................................................................5-5
5.1.7.1
Table Lookup and Interpolate Instructions...................................................5-5
5.1.7.2
Low-Power Stop Instruction............................................................................5-7