參數(shù)資料
型號(hào): M34559G6
廠商: Renesas Technology Corp.
英文描述: SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
中文描述: 單芯片4位微機(jī)的CMOS
文件頁數(shù): 80/148頁
文件大?。?/td> 1732K
代理商: M34559G6
Rev.1.04
REJ03B0188-0104
Aug 23, 2007
Page 80 of 146
4559 Group
Note 1. “R” represents read enabled, and “W” represents write enabled.
Note 2. To be invalid (K2
2
= “0”) key-on wakeup of ports P3
0
and P3
1
, set the registers K3
0
and K3
1
to “0.”
Note 3. To be invalid (K2
3
= “0”) key-on wakeup of ports P3
2
and P3
3
, set the registers K3
2
and K3
3
to “0.”
Key-on wakeup control register K0
at reset : 0000
2
at power down : state retained
R/W
TAK0/TK0A
K0
3
Ports P1
2
, P1
3
key-on wakeup
control bit
0
1
0
1
0
1
0
1
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
K0
2
Ports P1
0
, P1
1
key-on wakeup
control bit
K0
1
Ports P0
2
, P0
3
key-on wakeup
control bit
K0
0
Ports P0
0
, P0
1
key-on wakeup
control bit
Key-on wakeup control register K1
at reset : 0000
2
at power down : state retained
R/W
TAK1/TK1A
K1
3
Port P2
3
key-on wakeup control bit
0
1
0
1
0
1
0
1
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
K1
2
Port P2
2
key-on wakeup control bit
K1
1
Port P2
1
key-on wakeup control bit
K1
0
Port P2
0
key-on wakeup control bit
Key-on wakeup control register K2
at reset : 0000
2
at power down : state retained
R/W
TAK2/TK2A
K2
3
Ports P3
2
, P3
3
key-on wakeup
control bit (Note 3)
0
1
0
1
0
1
0
1
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Return by level
Return by edge
Key-on wakeup invalid
Key-on wakeup valid
K2
2
Ports P3
0
, P3
1
key-on wakeup
control bit (Note 2)
K2
1
INT pin return condition selection bit
K2
0
INT pin key-on wakeup control bit
Key-on wakeup control register K3
at reset : 0000
2
at power down : state retained
R/W
TAK3/TK3A
K3
3
Ports P3
2
, P3
3
return condition selection bit
(Note 3)
0
1
0
1
0
1
0
1
Return by level
Return by edge
Falling waveform/”L” level
Rising waveform/”H” level
Return by level
Return by edge
Falling waveform/”L” level
Rising waveform/”H” level
K3
2
Ports P3
2
, P3
3
valid waveform/level
selection bit (Note 3)
K3
1
Ports P3
0
, P3
1
return condition selection bit
(Note 2)
K3
0
Ports P3
0
, P3
1
valid waveform/level
selection bit (Note 2)
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