參數(shù)資料
型號: M34559G6
廠商: Renesas Technology Corp.
英文描述: SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
中文描述: 單芯片4位微機的CMOS
文件頁數(shù): 77/148頁
文件大?。?/td> 1732K
代理商: M34559G6
Rev.1.04
REJ03B0188-0104
Aug 23, 2007
Page 77 of 146
4559 Group
Note 1.
R
represents read enabled, and
W
represents write enabled.
Note 2. This function is valid only when the timer 1 count start synchronous circuit is selected (I1
0
=
1
).
Note 3. Port C output is invalid when CNTR input is selected for the timer 1 count source.
Timer control register PA
at reset : 0
2
at power down : 0
2
W
TAPP
PA
0
Prescaler control bit
0
1
Stop (state retained)
Operating
Timer control register W1
at reset : 0000
2
at power down : state retained
R/W
TAW1/TW1A
W1
3
Timer 1 count auto-stop circuit selection bit
(Note 2)
0
1
0
1
Timer 1 count auto-stop circuit not selected
Timer 1 count auto-stop circuit selected
Stop (state retained)
Operating
W1
1
W1
0
W1
2
Timer 1 control bit
Timer 1 count source selection bits (Note 3)
Count source
W1
1
0
0
PWM signal (PWMOUT)
0
1
Prescaler output (ORCLK)
1
0
Timer 3 underflow signal (T3UDF)
W1
0
1
1
CNTR input
Timer control register W2
at reset : 0000
2
at power down : 0000
2
R/W
TAW2/TW2A
W2
3
CNTR pin function control bit
0
1
0
1
0
1
0
1
CNTR pin output invalid
CNTR pin output valid
PWM signal “H” interval expansion function invalid
PWM signal “H” interval expansion function valid
Stop (state retained)
Operating
X
IN
input
Prescaler output (ORCLK)/2
W2
2
PWM signal
“H” interval expansion function control bit
W2
1
Timer 2 control bit
W2
0
Timer 2 count source selection bit
Timer control register W3
at reset : 0000
2
at power down : state retained
R/W
TAW3/TW3A
W3
3
Timer 3 count source selection bit
0
1
0
1
X
IN
input
Prescaler output (ORCLK)
Stop (initial state)
Operating
W3
1
W3
0
W3
2
Timer 3 control bit
Timer 3 count value selection bits
Count source
W3
1
0
0
Underflow every 8192 count
0
1
Underflow every 16384 count
1
0
Underflow every 32768 count
W3
0
1
1
Underflow every 65536 count
Timer control register W4
at reset : 0000
2
at power down : state retained
R/W
TAW4/TW4A
W4
3
Timer LC control bit
0
1
0
1
0
1
0
1
Stop (state retained)
Operating
Bit 4 (T3
4
) of timer 3
System clock (STCK)
CNTR output auto-control circuit not selected
CNTR output auto-control circuit selected
Falling edge
Rising edge
W4
2
Timer LC count source selection bit
W4
1
CNTR pin output auto-control circuit
selection bit
W4
0
CNTR pin input count edge selection bit
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