參數(shù)資料
型號(hào): M34559G6
廠商: Renesas Technology Corp.
英文描述: SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
中文描述: 單芯片4位微機(jī)的CMOS
文件頁(yè)數(shù): 65/148頁(yè)
文件大?。?/td> 1732K
代理商: M34559G6
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Rev.1.04
REJ03B0188-0104
Aug 23, 2007
Page 65 of 146
4559 Group
QzROM Writing Mode
In the QzROM writing mode, the user ROM area can be
rewritten while the microcomputer is mounted on-board by using
a serial pro-grammer which is applicable for this microcomputer.
Table 29 lists the pin description (QzROM writing mode) and
Figure 66 shows the pin connections.
Refer to Figure 67 for examples of a connection with a serial pro-
grammer.
Contact the manufacturer of your serial programmer for serial
pro-grammer. Refer to the user’s manual of your serial
programmer for details on how to use it.
Note 1. Note that the P2
0
/SEG
24
pin is pulled down internally by the MCU during the transition period (the period when V
PP
is
approximately 0.5 V
DD
to 1.3 V
DD
) when the programming power supply (V
PP
) is applied to the CNV
SS
pin. In addition, the
P2
0
/SEG
24
pin is high inpedance when V
PP
is approximately 1.3 V
DD
or grater.
Table 29 Pin description (QzROM writing mode)
Pin
Name
I/O
Function
V
DD
, V
SS
Power source, GND
Apply 2.7 to 4.7V to V
CC
, and 0V to V
SS
.
Reset input pin for active “L”. Reset occurs when RESET pin is hold
at an “L” level for 16 cycles or more of X
IN
.
Either connect an oscillator circuit or connect X
IN
and X
CIN
to V
SS
and leave X
OUT
and X
COUT
open.
RESET
Reset input
input
X
IN
, X
CIN
X
OUT
, X
COUT
D
0
D
5
P0
0
/SEG
16
P0
3
/SEG
19
P1
0
/SEG
20
P1
3
/SEG
23
P2
0
/SEG
24
(Note 1)
P2
3
/SEG
27
P3
0
/SEG
28
P3
3
/SEG
31
CNV
SS
D
4
D
3
Clock input
Clock output
input
output
I/O port
I/O
Input “H” or “L” level signal or leave the pin open.
V
PP
input
SDA input/output
SCLK input
input
I/O
input
QzROM programmable power source pin.
Serial data I/O pin.
Serial clock input pin.
D
2
PGM input
Voltage drop
detection circuit
enable
Segment output/
LCD power source/
Common output
Output port C/
Timer I/O
input
Read/program pulse input pin.
VDCE
input
Input “H” or “L” level signal
SEG
0
/V
LC3
SEG
2
/V
LC1
SEG
3
SEG
15
COM
0
COM
3
output
Either connect to an LCD panel or leave open.
C/CNTR
output
C/CNTR pin outputs “L” level.
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