Rev.1.04
REJ03B0188-0104
Aug 23, 2007
Page 4 of 146
4559 Group
PERFORMANCE OVERVIEW
Table 2
Performance overview
Parameter
Function
Number of basic instructions
Minimum instruction execution time
Memory sizes
135
0.5
μ
s (Oscillation frequency 6 MHz: high-speed through mode)
6144 words
×
10 bits
288 words
×
4 bits (including LCD display RAM 32 words
×
4 bits)
Six independent I/O ports.
The output structure can be switched by software.
Port D
5
is also used as INT pin.
ROM
RAM
D
0
D
5
I/O port
I/O
(Input is
examined by
skip decision.)
Output
D
6
, D
7
Two independent output ports.
Ports D
6
and D
7
are also used as X
CIN
and X
COUT
, respectively.
4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can
be switched by software.
Ports P0
0
P0
3
are also used as SEG
16
SEG
19
, respectively.
4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can
be switched by software.
Ports P1
0
P1
3
are also used as SEG
20
SEG
23
, respectively.
4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can
be switched by software.
Ports P2
0
P2
3
are also used as SEG
24
SEG
27
, respectively.
4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can
be switched by software.
Ports P3
0
P3
3
are also used as SEG
28
SEG
31
, respectively.
1-bit output; Port C is also used as CNTR pin.
8-bit timer with a reload register and carrier wave output auto-control function,
and has an event counter.
8-bit timer with two reload registers and carrier wave generation function.
16-bit timer, fixed dividing frequency (timer for clock count)
4-bit programmable timer with a reload register (for LCD clock generating)
16-bit timer, fixed dividing frequency (timer for monitor)
1/2, 1/3 bias
2, 3, 4 duty
4
32
2r
×
3, 2r
×
2, r
×
3, r
×
2 (r = 100 k
, (Ta = 25
°
C, Typical value))
P0
0
P0
3
I/O
P1
0
P1
3
I/O
P2
0
P2
3
I/O
P3
0
P3
3
I/O
C
Timer 1
Output
Timer
Timer 2
Timer 3
Timer LC
Watchdog timer
Selective bias value
Selective duty value
Common output
Segment output
Internal resistor for power
supply
Reset occurrence
Reset release
Skip occurrence
LCD control circuit
Voltage drop
detection circuit
Typ. 1.7 V (Ta=25 °C)
Typ. 1.8 V (Ta=25 °C)
Typ. 2.0 V (Ta=25 °C)
Built-in
4 sources (one for external, three for timers)
1 level
8 levels
CMOS silicon gate
52-pin plastic molded LQFP (PLQP0052JA-A)
-20 to 85 °C
1.8 to 5.5 V (It depends on operation source clock, oscillation frequency and
operation mode)
0.3 mA (Ta = 25 °C, V
DD
=
3 V, f(X
IN
) = 4 MHz, f(X
CIN
) = stop, f(RING) = stop,
f(STCK) = f(X
IN
)/8
5
μ
A (Ta = 25 °C, V
DD
=
3 V, f(X
CIN
) = 32 kHz)
0.1
μ
A (Ta = 25 °C, V
DD
=
5 V, output transistor is cut-off state)
Power-on reset circuit
Interrupt
Source
Nesting
Subroutine nesting
Device structure
Package
Operating temperature range
Power source voltage
Power
dissipation
(Typ. value)
At active mode
At clock operating mode
At RAM back-up