參數(shù)資料
型號: M34559G6
廠商: Renesas Technology Corp.
英文描述: SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
中文描述: 單芯片4位微機(jī)的CMOS
文件頁數(shù): 141/148頁
文件大小: 1732K
代理商: M34559G6
Rev.1.04
REJ03B0188-0104
Aug 23, 2007
Page 141 of 146
4559 Group
Recommended operating conditions
Note 1. At 1/2 bias: V
LC1
= V
LC2
= (1/2)V
LC3
At 1/3 bias: V
LC1
= (1/3)V
LC3
, V
LC2
= (2/3)V
LC3
Note 2. The average output current is the average value during 100ms.
Table 31 Recommended operating conditions 1 (Ta = –20
°
C to 85
°
C, V
DD
= 1.8 to 5.5 V, unless otherwise noted)
Symbol
Parameter
Conditions
Limits
Typ.
Unit
Min.
4
2.7
2
1.8
4
2.7
2
1.8
2.7
Max.
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
V
DD
Supply voltage
(with a ceramic resonator)
f(STCK)
6MHz
f(STCK)
4.4MHz
f(STCK)
2.2MHz
f(STCK)
1.1MHz
f(STCK)
4.8MHz
f(STCK)
3.2MHz
f(STCK)
1.6MHz
f(STCK)
0.8MHz
f(STCK)
4.4 MHz
V
V
DD
Supply voltage
(when an external clock is
used)
V
V
DD
Supply voltage
(when RC oscillation is used)
Supply voltage
(when quartz-crystal oscillation
is used)
Supply voltage
(when on-chip oscillation is
used)
RAM back-up voltage
Supply voltage
LCD power supply (Note 1)
“H” level input voltage
V
V
DD
f(STCK)
50 kHz
1.8
5.5
V
V
DD
1.8
5.5
V
V
RAM
V
SS
V
LC3
V
IH
(at RAM back-up)
1.6
5.5
V
V
V
V
0
1.8
V
DD
V
DD
V
DD
V
DD
P0, P1, P2, P3, D
0
D
5
X
IN
, X
CIN
0.8V
DD
0.7V
DD
0.85V
DD
RESET
INT
CNTR
P0, P1, P2, P3, D
0
D
5
X
IN
, X
CIN
0.85V
DD
V
DD
0.8V
DD
0
0
0
V
DD
0.2V
DD
0.3V
DD
0.3V
DD
V
IL
“L” level input voltage
V
RESET
INT
CNTR
P0, P1, P2, P3, D
0
D
5
0
0.15V
DD
0
0.15V
DD
20
10
30
15
10
5
20
10
24
12
10
4
15
7
5
2
40
40
40
40
I
OH(peak)
“H” level peak output current
V
DD
= 5V
V
DD
= 3V
V
DD
= 5V
V
DD
= 3V
V
DD
= 5V
V
DD
= 3V
V
DD
= 5V
V
DD
= 3V
V
DD
= 5V
V
DD
= 3V
V
DD
= 5V
V
DD
= 3V
V
DD
= 5V
V
DD
= 3V
V
DD
= 5V
V
DD
= 3V
mA
C/CNTR
I
OH(avg)
“H” level average output current
(Note 2)
P0, P1, P2, P3, D
0
D
5
mA
C/CNTR
I
OL(peak)
“L” level peak output current
P0, P1, P2, P3, D
0
D
7
, C/CNTR
mA
RESET
I
OL(avg)
“L” level average output current
(Note 2)
P0, P1, P2, P3, D
0
D
7
, C/CNTR
mA
RESET
Σ
I
OH(avg)
“H” level total average current
P0, C/CNTR
P1, P2, P3, D
0
D
5
P0, C/CNTR
mA
Σ
I
OL(avg)
“L” level total average current
mA
P1, P2, P3, D
0
D
7
, RESET
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