參數(shù)資料
型號: M34559G6
廠商: Renesas Technology Corp.
英文描述: SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
中文描述: 單芯片4位微機(jī)的CMOS
文件頁數(shù): 7/148頁
文件大?。?/td> 1732K
代理商: M34559G6
Rev.1.04
REJ03B0188-0104
Aug 23, 2007
Page 7 of 146
4559 Group
DEFINITION OF CLOCK AND CYCLE
Operation source clock
The operation source clock is the source clock to operate this
product. In this product, the following clocks are used.
Clock (f(X
IN
)) by the external ceramic resonator
Clock (f(X
IN
)) by the external RC oscillation
Clock (f(X
IN
)) by the external input
Clock (f(RING)) of the on-chip oscillator which is the internal
oscillator
Clock (f(X
CIN
)) by the external quartz-crystal oscillation
System clock (STCK)
The system clock is the basic clock for controlling this product.
The system clock is selected by the clock control register MR
shown as the table below.
Machine cycle
The machine cycle is the standard cycle required to execute the
instruction.
Instruction clock (INSTCK)
The instruction clock is the basic clock for controlling CPU. The
instruction clock (INSTCK) is a signal derived by dividing the
system clock (STCK) by 3. The one instruction clock cycle
generates the one machine cycle.
Note 1. The f(RING)/8 is selected after system is released from reset
Table 6
Table Selection of system clock
Register MR
MR
2
1
0
1
0
1
0
1
0
1
0
1
0
System clock
Operation mode
MR
3
1
1
0
0
1
1
0
0
1
1
0
0
MR
1
0
0
0
0
0
0
0
0
1
1
1
1
MR
0
0
0
0
0
1
1
1
1
0
0
0
0
f(STCK) = f(RING)/8
f(STCK) = f(RING)/4
f(STCK) = f(RING)/2
f(STCK) = f(RING)
f(STCK) = f(X
IN
)/8
f(STCK) = f(X
IN
)/4
f(STCK) = f(X
IN
)/2
f(STCK) = f(X
IN
)
f(STCK) = f(X
CIN
)/8
f(STCK) = f(X
CIN
)/4
f(STCK) = f(X
CIN
)/2
f(STCK) = f(X
CIN
)
Internal frequency divided by 8 mode
Internal frequency divided by 4 mode
Internal frequency divided by 2 mode
Internal frequency through mode
High-speed frequency divided by 8 mode
High-speed frequency divided by 4 mode
High-speed frequency divided by 2 mode
High-speed through mode
Low-speed frequency divided by 8 mode
Low-speed frequency divided by 4 mode
Low-speed frequency divided by 2 mode
Low-speed through mode
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