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6
INTERNAL MEMORY
6-6
32185/32186 Group Hardware Manual
Rev.1.10 REJ09B0235-0110 May 15, 07
<Upon exiting reset: H'0000>
b
Bit Name
Function
R
W
0
RAMWRCNT0
0: Enable write to area 0
R
W
(Area 0 RAM write disable control bit)
1: Disable write to area 0
1
RAMWRCNT1
0: Enable write to area 1
R
W
(Area 1 RAM write disable control bit)
1: Disable write to area 1
2
RAMWRCNT2
0: Enable write to area 2
R
W
(Area 2 RAM write disable control bit)
1: Disable write to area 2
3
RAMWRCNT3
0: Enable write to area 3
R
W
(Area 3 RAM write disable control bit)
1: Disable write to area 3
4
RAMWRCNT4
0: Enable write to area 4
R
W
(Area 4 RAM write disable control bit)
1: Disable write to area 4
5
RAMWRCNT5
0: Enable write to area 5
R
W
(Area 5 RAM write disable control bit)
1: Disable write to area 5
6
RAMWRCNT6
0: Enable write to area 6
R
W
(Area 6 RAM write disable control bit)
1: Disable write to area 6
7
RAMWRCNT7
0: Enable write to area 7
R
W
(Area 7 RAM write disable control bit)
1: Disable write to area 7
8
RAMWRCNT8
0: Enable write to area 8
R
W
(Area 8 RAM write disable control bit)
1: Disable write to area 8
9
RAMWRCNT9
0: Enable write to area 9
R
W
(Area 9 RAM write disable control bit)
1: Disable write to area 9
10
RAMWRCNT10
0: Enable write to area 10
R
W
(Area 10 RAM write disable control bit)
1: Disable write to area 10
11
RAMWRCNT11
0: Enable write to area 11
R
W
(Area 11 RAM write disable control bit)
1: Disable write to area 11
12
RAMWRCNT12
0: Enable write to area 12
R
W
(Area 12 RAM write disable control bit)
1: Disable write to area 12
13
RAMWRCNT13
0: Enable write to area 13
R
W
(Area 13 RAM write disable control bit)
1: Disable write to area 13
14
RAMWRCNT14
0: Enable write to area 14
R
W
(Area 14 RAM write disable control bit)
1: Disable write to area 14
15
RAMWRCNT15
0: Enable write to area 15
R
W
(Area 15 RAM write disable control bit)
1: Disable write to area 15
This register controls accesses for write to the RAM by enabling or disabling the access. Controlled by this
register are the accesses made by the CPU, DMA, SDI (tool), and NBD. If one of these modules attempted to
access any area for write that is disabled against write, the corresponding RAM write monitor interrupt status is
set to "1," with no data actually written to the RAM.
Before this register can be rewritten, the RAMWRCNTPRO bit in the RAM Write Disable Protect Register must
be "0."
b0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
b15
RAMWRCNT0 RAMWRCNT1
RAMWRCNT3 RAMWRCNT4 RAMWRCNT5
RAMWRCNT8
0000000000000000
RAMWRCNT15
RAMWRCNT14
RAMWRCNT13
RAMWRCNT12
RAMWRCNT11
RAMWRCNT10
RAMWRCNT9
RAMWRCNT7
RAMWRCNT6
RAMWRCNT2
6.3 Internal RAM Protect Function
RAM Write Disable Control Register (RAMWRCNT)
<Address: H’0080 0538>