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INTERRUPT CONTROLLER (ICU)
5
5-14
32185/32186 Group Hardware Manual
Rev.1.10 REJ09B0235-0110 May 15, 07
5.5.2 Processing by Internal Peripheral I/O Interrupt Handlers
(1) Branching to the interrupt handler
Upon accepting an interrupt request, the CPU branches to the EIT vector entry after performing the
hardware preprocessing as described in Section 4.3, “EIT Processing Procedure.” The EIT vector
entry for External Interrupt (EI) is located at the address H’0000 0080. This address is where the
instruction (not the jump address itself) for branching to the beginning of the interrupt handler routine
for external interrupt requests is written.
(2) Processing in the External Interrupt (EI) handler
A typical operation of the External Interrupt (EI) handler (for interrupts from internal peripheral I/O) is
shown in Figure 5.5.2.
[1] Saving each register to the stack
Save the BPC, PSW and general-purpose registers to the stack. Also, save the accumulator and
FPSR register to the stack as necessary.
[2] Reading the Interrupt Request Mask Register (IMASK) and saving to the stack
Read the Interrupt Request Mask Register and save its content to the stack.
[3] Reading the Interrupt Vector Register (IVECT)
Read the Interrupt Vector Register. This register holds the 16 low-order address bits of the ICU
vector table for the accepted interrupt request source that was stored in it when accepting an
interrupt request. When the Interrupt Vector Register is read, the following processing is
automatically performed in hardware:
The interrupt priority level of the accepted interrupt request (ILEVEL) is set in the IMASK
register as a new IMASK value. (Interrupts with lower priority levels than that of the
accepted interrupt request source are masked.)
The accepted interrupt request source is cleared (not cleared for level-recognized interrupt
request sources).
The interrupt request (EI) to the CPU core is dropped.
Internal sequencer of ICC is activated to start internal processing (interrupt priority
resolution).
[4] Reading and overwriting the Interrupt Request Mask Register (IMASK)
Read the Interrupt Request Mask Register and overwrite it with the read value. This write to the
IMASK register causes the following processing to be automatically performed in hardware:
The interrupt request (EI) to the CPU core is dropped.
Internal sequencer of ICC is activated to start internal processing (interrupt priority resolution).
[5] Reading the ICU vector table
Read the ICU vector table for the accepted interrupt request source. The relevant ICU vector table
address can be obtained by zero-extending the content of the Interrupt Vector Register that was
read in [3] (i.e., the 16 low-order address bits of the ICU vector table for the accepted interrupt
request source). The ICU vector table must have set in it the start address of the interrupt handler
for the interrupt request source concerned.)
5.5 Description of Interrupt Operation