
SERIAL INTERFACE
12
12-60
32185/32186 Group Hardware Manual
Rev.1.10 REJ09B0235-0110 May 15, 07
Figure 12.7.7 Delay in Receive Timing
12.7.5 Start Bit Detection and Data Sampling Timing during UART Reception
The start bit is sampled synchronously with the internal BRG output. If the received signal remains "L" for
8 BRG output cycles after the falling edge of the start bit, the CPU recognizes that part of the received
signal as the start bit and starts latching the received data another 8 cycles after that, beginning with the
LSB (first bit). If some sampled part of the received signal is "H" before being determined to be the start bit,
the CPU starts hunting the falling edge of the received signal again. Because the start bit is sampled
synchronously with the internal BRG output, there is a delay equivalent to one BRG output cycle at maxi-
mum. The subsequent received data is latched into the internal circuit with that delayed timing.
Figure 12.7.5 Start Bit Detection and Data Sampling Timing
Figure 12.7.6 Example of an Invalid Start Bit (Not Received)
Internal
BRG output
RXD
LSB data
8 cycles
Note: This diagram does not show detailed timing information.
8 cycles
16 cycles
Data sampling
(Data for first bit)
Start bit determined
Internal BRG output
RXD
8 cycles
Note: This diagram does not show detailed timing information.
Internal RXD
Internal BRG output
RXD
Delay equivalent to one BRG output cycle at maximum
12.7 Receive Operation in UART Mode