DMAC
9
9-23
32185/32186 Group Hardware Manual
Rev.1.10 REJ09B0235-0110 May 15, 07
9.2 DMAC Related Registers
DMA8 Channel Control Register 1 (DM8CNT1)
<Address: H’0080 0449>
9
1011121314
b15
b8
REQESEL8
00000000
SADBN8
DADBN8
<Upon exiting reset: H’00>
b
Bit Name
Function
R
W
8, 9
SADBN8
00: Bank 0 (A14=0, A15=0)
R
W
Source address bank select bit
01: Bank 1 (A14=0, A15=1)
(Note 1) (Note 2)
10: Settings inhibited
11: Settings inhibited
10, 11
DADBN8
00: Bank 0 (A14=0, A15=0)
R
W
Destination address bank select bit
01: Bank 1 (A14=0, A15=1)
(Note 1) (Note 2)
10: Settings inhibited
11: Settings inhibited
12–15
REQESEL8
0000: CAN1_S0/S31
R
W
Extended DMA8 transfer request source select bit
0001: MJT(TOU0_6irq)
0010: One DMA7 transfer completed
0011: Common 1) MJT (input event bus 1)
0100: Common 2) MJT (input event bus 3)
0101: Common 3) MJT (output event bus 2)
0110: Common 4) MJT (output event bus 3)
0111: Common 5) AD0 conversion completed
1000: Common 6) MJT (TIN0S)
1001: Common 7) MJT (TIO8_udf)
1010: Common 8) MJT (TIN30S)
1011: Common 9) MJT (TIO9_udf)
1100: Common 10) Settings inhibited
1101: DRI (latch event counter_udf)
1110: DRI (DEC3_udf)
1111: Settings inhibited
Note 1: No transfer over the bank is possible. Even when the address is incremented at the breakpoint of the bank and the
source/destination addresses go over the bank, the source address bank select/destination address bank select bits are
not incremented, and the bank head corresponds to the source address/destination address.
Note 2: Because Bank1 does not exist in the 32185, setting Bank1 (A14=0, A15=1) is prohibited.