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10.8 TOU (Output-Related 24-Bit Timer)
MULTIJUNCTION TIMERS
10
10-177
32185/32186 Group Hardware Manual
Rev.1.10 REJ09B0235-0110 May 15, 07
To update PWM period correctly, take either one of the following measures.
Identify the completion timing of PWM period by reading counter value at writing reload 1 register and
reload 0 register, and then start writing reload 1 register and reload 0 register without crossing PWM period.
When writing to reload 1 register and reload 0 register by using interruption, set the prescaler value of
counter as small as possible. By doing this, write to reload 1 register and reload 0 register later than the
counter to be H'FFFF in the PWM period.
Writing reload 1 register and reload 0 register is performed under the period, less than one time per PWM
period. (Extend the reload register's rewrite period against PWM period.)
(3) Notes on using TOU PWM output mode
The following describes precautions to be observed when using TOU PWM output mode.
If the timer is enabled by external input in the same clock period as count is disabled by writing to the
enable bit, the latter has priority so that count is disabled.
If the counter is accessed for read to the cycle of underflow, the counter value is read out as H'FFFF but
changes to “ reload register value -1” at the next count clock timing.
Because the timer operates synchronously with the count clock, a count clock-dependent delay is in-
cluded before F/F output is inverted after the timer is enabled.
Because a 0% or 100% duty-cycle needs to be determined when reloading the counter, there is a one count
clock equivalent delay before F/F is inverted and an interrupt or DMA transfer request is generated. How-
ever, startup requests to other timers are not delayed. For details, see Section 10.8.19, “0% or 100% Duty-
Cycle Wave Output during PWM Output and Single-shot PWM Output Modes.”
Figure 10.8.9 Update timing of PWM period
Count clock
Counter
H'FFFF
H'0000
F/F output
Underflow
(1st time)
Reload 0 register
(Note 2)
(Note 1)
Reload 1 register
PWM period
(Note 1)
Note 1: The value that "the reload 0 register -1" is reloaded.
Note 2: The value that "the reload 1 buffer -1" is reloaded.
Notes: .
:
Indicate sampling points.
. This diagram does not show detailed timing information.
Reload 1 buffer
Condition 1
Old PWM output period
Condition 2
New PWM putput period
Reloading "reload 0 register"
(Loading PWM period)
Reloading "reload 0 register"
(Loading PWM period)
Underflow
(2nd time)
Underflow
(2nd time)