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SUMMARY OF PRECAUTIONS
Appendix 4
Appendix 4-10
32185/32186 Group Hardware Manual
Rev.1.10 REJ09B0235-0110 May 15, 07
Appendix 4.9 Notes on Multijunction Timers
Appendix 4.9.3 Notes on using TOP continuous output mode
The following describes precautions to be observed when using TOP continuous output mode.
If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable
bit, the latter has priority so that count is disabled.
If the counter is accessed for read at the cycle of underflow, the counter value is read as H’FFFF but changes
to "reload register value -1" at the next count clock timing.
Because the timer operates synchronously with the count clock, a count clock-dependent delay is included
before F/F output is inverted after the timer is enabled.
Appendix 4.9.4 Notes on using TIO measure free-run/ clear input modes
The following describes precautions to be observed when using TIO measure free-run/ clear input modes.
If measure event input and write to the counter occur in the same clock period, the write value is set in the
counter while at the same time latched into the measure register.
Appendix 4.9.5 Notes on using TIO PWM output mode
The following describes precautions to be observed when using TIO PWM output mode.
If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable
bit, the latter has priority so that count is disabled.
If the counter is accessed for read at the cycle of underflow, the counter value is read as H’FFFF but
changes to "reload register value -1" at the next count clock timing.
Because the timer operates synchronously with the count clock, up to one count clock-dependent delay is
generated before F/F output is inverted after writing to the enable bit.
Appendix 4.9.6 Notes on using TIO single-shot output mode
The following describes precautions to be observed when using TIO single-shot output mode.
If the counter stops due to an underflow in the same clock period as the timer is enabled by external input,
the former has priority so that the counter stops.
If the counter stops due to an underflow in the same clock period as count is enabled by writing to the enable
bit, the latter has priority so that count is enabled.
If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable
bit, the latter has priority so that count is disabled.
Because the timer operates synchronously with the count clock, up to one count clock-dependent delay is
generated before F/F output is inverted after writing to the enable bit.