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10.8 TOU (Output-Related 24-Bit Timer)
MULTIJUNCTION TIMERS
10
10-162
32185/32186 Group Hardware Manual
Rev.1.10 REJ09B0235-0110 May 15, 07
TOU0_0 Reload 1 Register (TOU00RL1)
<Address: H'0080 0794>
TOU0_1 Reload 1 Register (TOU01RL1)
<Address: H'0080 079C>
TOU0_2 Reload 1 Register (TOU02RL1)
<Address: H'0080 07A4>
TOU0_3 Reload 1 Register (TOU03RL1)
<Address: H'0080 07AC>
TOU0_4 Reload 1 Register (TOU04RL1)
<Address: H'0080 07B4>
TOU0_5 Reload 1 Register (TOU05RL1)
<Address: H'0080 07BC>
TOU0_6 Reload 1 Register (TOU06RL1)
<Address: H'0080 07C4>
TOU0_7 Reload 1 Register (TOU07RL1)
<Address: H'0080 07CC>
TOU1_0 Reload 1 Register (TOU10RL1)
<Address: H'0080 0B94>
TOU1_1 Reload 1 Register (TOU11RL1)
<Address: H'0080 0B9C>
TOU1_2 Reload 1 Register (TOU12RL1)
<Address: H'0080 0BA4>
TOU1_3 Reload 1 Register (TOU13RL1)
<Address: H'0080 0BAC>
TOU1_4 Reload 1 Register (TOU14RL1)
<Address: H'0080 0BB4>
TOU1_5 Reload 1 Register (TOU15RL1)
<Address: H'0080 0BBC>
TOU1_6 Reload 1 Register (TOU16RL1)
<Address: H'0080 0BC4>
TOU1_7 Reload 1 Register (TOU17RL1)
<Address: H'0080 0BCC>
<Upon exiting reset: Undefined>
b
Bit Name
Function
R
W
0–15
TOU00RL1–TOU07RL1,
16-bit reload register value
R
W
TOU10RL1–TOU17RL1
Note: These registers must always be accessed in halfwords.
During PWM output and single-shot PWM output modes, TOU operates as a 16-bit timer. Use the reload 1
register to set the 16-bit value to be loaded into the counter when the count value set in the reload 1 register has
underflowed.
The content of " the reload 1 register -1" is loaded into the counter synchronously with the count clock at the
following timing:
At the next cycle when the count value set in the reload 0 register has underflowed in PWM output mode
Simply because data is written to the reload register does not mean that the data is loaded into the counter. The
counter is loaded with data in only the above cases.
If the value ‘H'FFFF’ is set in the reload register, F/F output will not be inverted, making it possible to produce
a 0% or 100% duty-cycle PWM output. For details, see Section 10.8.19, “0% or 100% Duty-Cycle Wave Output
during PWM Output and Single-shot PWM Output Modes.”
During single-shot output, delayed single-shot output and continuous output modes, the reload 0 and reload 1
registers are combined for use as a 24-bit reload register. For details, see Section 10.8.7, Paragraph (1), “TOU
reload registers during single-shot output, delayed single-shot output and continuous output modes.”
b0
12
34
56
78
9
10
11
12
13
14
b15
TOU00RL1–TOU07RL1, TOU10RL1–TOU17RL1
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