參數(shù)資料
型號： ISP1760
廠商： NXP Semiconductors N.V.
英文描述： Hi-Speed Universal Serial Bus host controller for embedded applications
中文描述： 高速嵌入式應(yīng)用的通用串行總線主控制器
文件頁數(shù)： 56/105頁
文件大?。?/td> 449K
代理商： ISP1760
9397 750 13257
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 8 November 2004
56 of 105
Philips Semiconductors
ISP1760
Embedded Hi-Speed USB host controller
Multiple transfers are scheduled to the shared memory for various endpoints by traversing
the next link pointer provided by the EHCI data structure, until it reaches the terminate bit
in a microframe. If a schedule is enabled, the Host Controller starts executing from the
ISO schedule, before it goes to the INTL schedule, and then to the ATL schedule.
The EHCI periodic and asynchronous lists are traversed by the software according to the
EHCI traversal rule, and executed only from the asynchronous schedule after it
encounters the end of the periodic schedule. The Host Controller traverses the ISO, INTL
and ATL schedules. It fetches the element and begins traversing the graph of linked
schedule data structures.
The last bit identifies the end of the schedule for each type of transfer, indicating the rest
of the channels are empty. Once a transition is completed, the Host Controller executes
from the next transfer descriptor in the schedule until the end of the microframe.
The completion of a transfer is indicated to the software by the interrupt that can be
grouped over the various PTDs by using the AND or OR registers that are available for
each schedule type (ISO, INTL and ATL). These registers are simple logic registers to
decide the group and individual PTDs that can interrupt the CPU for a schedule, when the
logical conditions of the done bit is true in the shared memory that completes the interrupt.
Interrupts are of four types and the latency can be programmed in multiples of
μ
SOF
(125
μ
s).
ISO interrupt
INTL interrupt
ATL Interrupt
SOF—start of frame interrupt for the data transfer.
A static PTD that schedules inside the ISP1760 shared memory allows using the
NextPTD mechanism that will enable the Host Controller driver to schedule the multiple
PTDs that are of single endpoint and reduce the interrupt to the CPU.
The NextPTD traversal rules defined by the ISP1760 hardware are:
1. Start the ATL header traversal.
2. If the current PTD is active and not done, perform the transaction.
3. Follow the next link pointer.
4. If PTD is not active and done, jump to the next PTD.
5. If the next link pointer is NULL, it means the end of the traversal.
相關(guān)PDF資料
PDF描述
ISP1761 Hi-Speed Universal Serial Bus On-The-Go controller
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ISP1761ET Hi-Speed Universal Serial Bus On-The-Go controller
ISP2100A Telecommunication IC
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISP1760BE 制造商:NXP Semiconductors 功能描述:CONTROLLER USB HOST SMD LQFP128 制造商:ST-Ericsson 功能描述:IC CONTROLLER USB HOST 128LQFP
ISP1760BE,518 功能描述:輸入/輸出控制器接口集成電路 USB HOST CONTROLLER RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray
ISP1760BE,551 功能描述:輸入/輸出控制器接口集成電路 USB HS HOST CONTRLLR RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray
ISP1760BE,557 功能描述:USB 接口集成電路 DO NOT USE ORDER -S OR -T PART RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1760BE518 制造商:ST-Ericsson 功能描述:IC CONTROLLER USB HOST 128LQFP
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