參數(shù)資料
型號(hào)： ISP1760
廠商： NXP Semiconductors N.V.
英文描述： Hi-Speed Universal Serial Bus host controller for embedded applications
中文描述： 高速嵌入式應(yīng)用的通用串行總線主控制器
文件頁(yè)數(shù)： 39/105頁(yè)
文件大小： 449K
代理商： ISP1760
9397 750 13257
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 8 November 2004
39 of 105
Philips Semiconductors
ISP1760
Embedded Hi-Speed USB host controller
When a bit in the PTD Skip Map is set to logic 1 that PTD will be skipped although its V bit
may be set. The information in that PTD is not processed. For example, NextPTDPointer
will not affect the order of processing of PTDs. The Skip bit should not be normally set on
the position indicated by NextPTDPointer.
8.2.16
ATL PTD Last PTD register (R/W: 0158h)
The bit description of the ATL PTD Last PTD register is given in
Table 32
.
Once the LastPTD bit corresponding to a PTD is set, this will be the last PTD processed
(checking V = 1) in that PTD category. Subsequently, the process will restart with the first
PTD (of that group). This is useful to reduce the time in which all the PTDs (the respective
memory space) would be checked, especially if only a few PTDs are defined. The
LastPTD bit must be normally set to a higher position than any other position indicated by
the NextPTDPointer from an active PTD.
8.3 Configuration registers
8.3.1
HW Mode Control register (R/W: 0300h)
Table 33
shows the bit allocation of the register.
Table 31:
Bit
31 to 0 ATL_PTD_SKIP
_MAP[31:0]
ATL PTD Skip Map register: bit description
Symbol
Access
R/W
Value
FFFF FFFFh
Description
ATL PTD Skip Map
: Skip map for each of
the 32 PTDs for the ATL transfer
Table 32:
Bit
31 to 0
ATL PTD Last PTD register: bit description
Symbol
Access
ATL_PTD_
LAST_PTD
[31:0]
Value
0000 0000h
Description
ATL PTD Last PTD
: Last PTD of the
32 PTDs as indicated by the 32 bitmap.
1h —
One PTD in ATL
2h —
Two PTDs in ATL
4h —
Three PTDs in ATL.
R/W
Table 33:
Bit
Symbol
HW Mode Control register: bit allocation
31
30
ALL_ATX_
RESET
0
R/W
R/W
23
22
29
28
27
26
25
24
reserved
[1]
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
0
0
0
0
0
0
0
R/W
21
R/W
20
R/W
19
R/W
18
R/W
17
R/W
16
reserved
[1]
0
0
0
0
0
0
0
0
R/W
15
R/W
14
R/W
13
R/W
12
R/W
11
R/W
10
R/W
9
R/W
8
ANA_DIGI
_OC
0
R/W
reserved
[1]
DATA_BUS
_WIDTH
1
R/W
Reset
Access
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
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