參數(shù)資料
型號: ISP1760
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus host controller for embedded applications
中文描述: 高速嵌入式應(yīng)用的通用串行總線主控制器
文件頁數(shù): 27/105頁
文件大?。?/td> 449K
代理商: ISP1760
9397 750 13257
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 8 November 2004
27 of 105
Philips Semiconductors
ISP1760
Embedded Hi-Speed USB host controller
8.
Registers
Table 5
shows the bit description of the registers.
All registers range from 0000h to 03FFh. These registers can be read or written as
double word, that is 32-bit data. In the case of a 16-bit data bus width, two subsequent
accesses are necessary to complete the register read or write cycle.
Operational registers range from 0000h to 01FFh. Configuration registers range from
0300h to 03FFh.
Table 5:
Address
EHCI capability registers
0000h
0002h
0004h
0008h
EHCI operational registers
0020h
0024h
0028h
002Ch
0030h
0060h
0064h
0130h
0134h
0138h
0140h
0144h
0148h
0150h
0154h
0158h
0200h–02FFh
Configuration registers
0300h
0304h
0308h
030Ch
0330h
0334h
0338h
033Ch
Register overview
Register
Reset value
References
CAPLENGTH
HCIVERSION
HCSPARAMS
HCCPARAMS
20h
0100h
0000 0011h
0000 0086h
Section 8.1.1 on page 28
Section 8.1.2 on page 28
Section 8.1.3 on page 28
Section 8.1.4 on page 29
USBCMD
USBSTS
USBINTR
FRINDEX
CTRLDSSEGMENT
CONFIGFLAG
PORTSC1
ISO PTD Done Map
ISO PTD Skip Map
ISO PTD Last PTD
INT PTD Done Map
INT PTD Skip Map
INT PTD Last PTD
ATL PTD Done Map
ATL PTD Skip Map
ATL PTD Last PTD
reserved
0008 0000h
0000 1000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 2000h
0000 0000h
FFFF FFFFh
0000 0000h
0000 0000h
FFFF FFFFh
0000 0000h
0000 0000h
FFFF FFFFh
0000 0000h
-
Section 8.2.1 on page 30
Section 8.2.2 on page 31
Section 8.2.3 on page 32
Section 8.2.4 on page 33
Section 8.2.5 on page 34
Section 8.2.6 on page 34
Section 8.2.7 on page 35
Section 8.2.8 on page 36
Section 8.2.9 on page 37
Section 8.2.10 on page 37
Section 8.2.11 on page 37
Section 8.2.12 on page 38
Section 8.2.13 on page 38
Section 8.2.14 on page 38
Section 8.2.15 on page 38
Section 8.2.16 on page 39
-
HW Mode Control
Chip ID
Scratch
SW Reset
DMA Configuration
Buffer Status
ATL Done Timeout
Memory
0000 0000h
0001 1761h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
Section 8.3.1 on page 39
Section 8.3.2 on page 41
Section 8.3.3 on page 41
Section 8.3.4 on page 41
Section 8.3.5 on page 42
Section 8.3.6 on page 43
Section 8.3.7 on page 44
Section 8.3.8 on page 44
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