參數(shù)資料
型號(hào)： ISP1760
廠商： NXP Semiconductors N.V.
英文描述： Hi-Speed Universal Serial Bus host controller for embedded applications
中文描述： 高速嵌入式應(yīng)用的通用串行總線主控制器
文件頁(yè)數(shù)： 33/105頁(yè)
文件大?。?/td> 449K
代理商： ISP1760
9397 750 13257
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 8 November 2004
33 of 105
Philips Semiconductors
ISP1760
Embedded Hi-Speed USB host controller
[1]
The reserved bits should always be written with the reset value.
[1]
For details on register bit description, refer to Enhanced Host Controller Interface Specification for Universal
Serial Bus Rev. 1.0
8.2.4
FRINDEX register (R/W: 002Ch)
The Frame Index (FRINDEX) register is used by the Host Controller to index into the
periodic frame list. The register updates every 125
μ
s (once each microframe). Bits n to 3
are used to select a particular entry in the Periodic Frame List during periodic schedule
execution. The number of bits used for the index depends on the size of the frame list as
set by the system software in the FLS (Frame List Size) field of the USBCMD register.
This register must be written as a Double Word. A Word-only write (16-bit mode) produces
undefined results. This register cannot be written unless the Host Controller is in the
halted state as indicated by the HCH (HCHalted) bit. A write to this register while the RS
(Run/Stop) bit is set produces undefined results. Writes to this register also affect the SOF
value. The bit allocation is given in
Table 18
.
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
23
22
21
20
19
18
17
16
reserved
[1]
0
0
0
0
0
0
0
0
R/W
15
R/W
14
R/W
13
R/W
12
R/W
11
R/W
10
R/W
9
R/W
8
reserved
[1]
0
0
0
0
0
0
0
0
R/W
7
R/W
6
R/W
5
R/W
4
R/W
3
FLRE
0
R/W
R/W
2
PCIE
0
R/W
R/W
1
R/W
0
reserved
[1]
reserved
[1]
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Table 17:
Bit
31 to 4
3
USBINTR register: bit description
Symbol
Description
[1]
-
reserved
FLRE
Frame List Rollover Enable
: When this bit is set and the FLR bit in the
USBSTS register is set, the Host Controller issues an interrupt. The
interrupt is acknowledged by software clearing bit FLR.
PCIE
Port Change Interrupt Enable
: When this bit is set and the PCD bit in the
USBSTS register is set, the Host Controller issues an interrupt. The
interrupt is acknowledged by software clearing bit PCD.
-
reserved
2
1 to 0
Table 18:
Bit
Symbol
Reset
Access
FRINDEX register: bit allocation
31
30
29
28
27
26
25
24
reserved
[1]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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ISP1760BE,551 功能描述:輸入/輸出控制器接口集成電路 USB HS HOST CONTRLLR RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray
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