參數(shù)資料
型號(hào): ISP1760
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus host controller for embedded applications
中文描述: 高速嵌入式應(yīng)用的通用串行總線主控制器
文件頁(yè)數(shù): 29/105頁(yè)
文件大?。?/td> 449K
代理商: ISP1760
9397 750 13257
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 8 November 2004
29 of 105
Philips Semiconductors
ISP1760
Embedded Hi-Speed USB host controller
[1]
For details on register bit description, refer to Enhanced Host Controller Interface Specification for Universal
Serial Bus Rev. 1.0
8.1.4
HCCPARAMS register (R: 0008h)
The Host Controller Capability Parameters (HCCPARAMS) register is a four-byte register,
and the bit allocation is given in
Table 10
.
Bit
Symbol
23
22
21
20
19
18
17
16
DPN[3:0]
reserved
P_INDI
CATOR
0
R
8
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
0
R
15
0
R
14
0
R
13
0
R
12
0
R
11
0
R
10
0
R
9
N_CC[3:0]
N_PCC[3:0]
0
R
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
2
N_PORTS[3:0]
0
R
0
R
1
0
R
0
PRR
0
R
reserved
PPC
1
R
0
R
0
R
0
R
0
R
1
R
Table 9:
Bit
31 to 24
23 to 20
HCSPARAMS register: bit description
Symbol
Description
[1]
-
reserved; write logic 0
DPN[3:0]
Debug Port Number
: This field identifies which of the Host
Controller ports is the debug port.
-
reserved; write logic 0
P_INDICATOR
Port Indicators
: This bit indicates whether the ports support port
indicator control.
N_CC[3:0]
Number of Companion Controller
: This field indicates the number
of companion controllers associated with this Hi-Speed USB Host
Controller.
N_PCC[3:0]
Number of Ports per Companion Controller
: This field indicates
the number of ports supported per companion Host Controller.
PRR
Port Routing Rules
: This field indicates the method used for
mapping ports to the companion controllers.
-
reserved; write logic 0
PPC
Port Power Control
: This field indicates whether the Host Controller
implementation includes port power control.
N_PORTS[3:0]
N_Ports
: This field specifies the number of physical downstream
ports implemented on this Host Controller.
19 to 17
16
15 to 12
11 to 8
7
6 to 5
4
3 to 0
Table 10:
Bit
Symbol
Reset
Access
HCCPARAMS register: bit allocation
31
30
29
28
27
26
25
24
reserved
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
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