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Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 8 November 2004
48 of 105
Philips Semiconductors
ISP1760
Embedded Hi-Speed USB host controller
[1]
For a 32-bit operation, the default wake-up counter value is 10
μ
s. For a 16-bit operation, the wake-up
counter value is 50 ms. In the 16-bit operation, read and write back the same value on initialization.
8.3.12
Port 1 Control register (R/W: 0374h)
The values read from the lower 16 bits and the upper 16 bits of this register are always the
same.
Table 52
shows the bit allocation of the register.
10
VBATDET_
PWR
V
BAT
Detector Powered
: Controls the power to the V
BAT
detector.
0 —
V
BAT
detector is powered or enabled in suspend
1 —
V
BAT
detector is not powered or disabled in suspend.
reserved; write logic 0
BIAS Circuits Powered
: Controls the power to internal BIAS circuits.
0 —
Internal BIAS circuits are not powered in suspend
1 —
Internal BIAS circuits are powered in suspend.
9 to 6
5
-
BIASEN
4
VREG_ON
V
REG
Powered
: Enables or disables the internal 3.3 V and 1.8 V
regulators when the ISP1760 is in suspend.
0 —
Internal regulators are powered in suspend
1 —
Internal regulators are not powered in suspend.
OC3_N Powered
: Controls the powering of the overcurrent detection
circuitry for port 3.
0 —
Overcurrent detection is powered on or enabled during suspend.
1 —
Overcurrent detection is powered off or disabled during suspend.
This may be useful when connecting a faulty device while the system is
in standby.
OC2_N Powered
: Controls the powering of the overcurrent detection
circuitry for port 2.
0 —
Overcurrent detection powered-on or enabled during suspend.
1 —
Overcurrent detection powered-off or disabled during suspend.
This may be useful when connecting a faulty device while the system is
in standby.
OC1_N Powered
: Controls the powering of the overcurrent detection
circuitry for port 1.
0 —
Overcurrent detection powered-on or enabled during suspend.
1 —
Overcurrent detection powered-off or disabled during suspend.
This may be useful when connecting a faulty device while the system is
in standby.
Host Controller Clock Enabled
: Controls internal clocks during
suspend.
0 —
Clocks are disabled during suspend. This is the default value. Only
the LazyClock of 100 kHz
±
40 % will be left running in suspend if this
bit is logic 0. If clocks are stopped during suspend, CLKREADY IRQ will
be generated when all clocks are running stable.
1 —
All clocks are enabled even in suspend.
3
OC3_PWR
2
OC2_PWR
1
OC1_PWR
0
HC_CLK_
EN
Table 51:
Bit
[1]
Power Down Control register: bit description
…continued
Symbol
Description