參數(shù)資料
型號(hào): ISP1760
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus host controller for embedded applications
中文描述: 高速嵌入式應(yīng)用的通用串行總線主控制器
文件頁(yè)數(shù): 52/105頁(yè)
文件大?。?/td> 449K
代理商: ISP1760
9397 750 13257
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 8 November 2004
52 of 105
Philips Semiconductors
ISP1760
Embedded Hi-Speed USB host controller
[1]
The reserved bits should always be written with the reset value.
Bit
Symbol
15
14
13
12
11
10
9
8
reserved
[1]
ISO_IRQ_
E
0
R/W
1
ATL_IRQ
_E
0
R/W
0
SOFITLINT
_E
0
R/W
Reset
Access
Bit
Symbol
0
0
0
0
0
0
R/W
7
R/W
6
CLK
R/W
5
R/W
4
R/W
3
R/W
2
INT_IRQ_E
READY _E
0
R/W
HCSUSP_
E
0
R/W
reserved
[1]
DMAEOT
INT _E
0
R/W
reserved
[1]
Reset
Access
0
0
0
0
R/W
R/W
R/W
R/W
Table 57:
Bit
31 to 10
9
Interrupt Enable register: bit description
Symbol
Description
-
reserved; write logic 0
ISO_IRQ_E
ISO IRQ Enable
: Controls the IRQ assertion because of completing
one or more ISO PTDs matching the ISO IRQ Mask AND or
ISO IRQ Mask OR register bits combination.
0 —
No IRQ will be asserted because of completing ISO PTDs
1 —
IRQ will be asserted.
For details, see
Section 7.4
.
ATL_IRQ_E
ATL IRQ Enable
: Controls the IRQ assertion because of completing
one or more ATL PTDs matching the ATL IRQ Mask AND or
ATL IRQ Mask OR register bits combination.
0 —
No IRQ will be asserted because of completing ATL PTDs
1 —
IRQ will be asserted.
For details, see
Section 7.4
.
INT_IRQ_E
INT IRQ Enable
: Controls the IRQ assertion because of completing
one or more INT PTDs matching the INT IRQ Mask AND or
INT IRQ Mask OR register bits combination.
0 —
No IRQ will be asserted because of completing INT PTDs
1 —
IRQ will be asserted.
For details, see
Section 7.4
.
CLKREADY
_E
signals are running stable. Useful after power-on or wake-up.
0 —
No IRQ will be generated after a CLKREADY_E event has
occurred
1 —
IRQ will be generated after a CLKREADY_E event.
HCSUSP_E
Host Controller Suspend Enable
: Enables the IRQ generation when
the Host Controller enters suspend mode.
0 —
No IRQ will be generated because of the Host Controller entering
suspend mode
1 —
IRQ will be generated at the Host Controller entering suspend
mode.
8
7
6
Clock Ready Enable
: Enables the IRQ assertion when internal clock
5
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