參數(shù)資料
型號(hào): ISP1760
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus host controller for embedded applications
中文描述: 高速嵌入式應(yīng)用的通用串行總線主控制器
文件頁(yè)數(shù): 54/105頁(yè)
文件大小: 449K
代理商: ISP1760
9397 750 13257
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 8 November 2004
54 of 105
Philips Semiconductors
ISP1760
Embedded Hi-Speed USB host controller
8.4.6
ISO IRQ Mask AND register (R/W: 0324h)
Each bit of this register corresponds to one of the 32 ISO PTDs defined, and is a
hardware IRQ mask for each PTD done map. For details, see
Section 7.4
.
Table 61
provides the bit description of the register.
8.4.7
INT IRQ Mask AND register (R/W: 0328h)
Each bit of this register (see
Table 62
) corresponds to one of the 32 INT PTDs defined,
and is a hardware IRQ mask for each PTD done map. For details, see
Section 7.4
.
8.4.8
ATL IRQ Mask AND register (R/W: 032Ch)
Each bit of this register corresponds to one of the 32 ATL PTDs defined, and is a
hardware IRQ mask for each PTD done map. For details, see
Section 7.4
.
Table 63
shows the bit description of the register.
Table 60:
Bit
31 to 0 ATL_IRQ_
MASK_OR
[31:0]
ATL IRQ Mask OR register: bit description
Symbol
Access
Value
R/W
0000 0000h
ATL IRQ Mask OR
: Represents a direct map for ATL
PTDs 31 to 0.
0 —
No OR condition defined between the ATL
PTDs
1 —
The bits corresponding to certain PTDs are set
to logic 1 to define a certain OR condition.
Description
Table 61:
Bit
31 to 0 ISO_IRQ_
MASK_
AND[31:0]
ISO IRQ Mask AND register: bit description
Symbol
Access
Value
R/W
0000 0000h
Description
ISO IRQ Mask AND
: Represents a direct map for
ISO PTDs 31 to 0.
0 —
No AND condition defined between ISO PTDs
1 —
The bits corresponding to certain PTDs are set
to logic 1 to define a certain AND condition
between the 32 INT PTDs.
Table 62:
Bit
31 to 0 INT_IRQ_
MASK_
AND[31:0]
INT IRQ Mask AND register: bit description
Symbol
Access
Value
R/W
0000 0000h
INT IRQ Mask AND
: Represents a direct map for
INT PTDs 31 to 0.
0 —
No OR condition defined between INT PTDs
1 —
The bits corresponding to certain PTDs are set
to logic 1 to define a certain AND condition between
the 32 INT PTDs.
Description
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