參數(shù)資料
型號(hào): ISP1760
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus host controller for embedded applications
中文描述: 高速嵌入式應(yīng)用的通用串行總線主控制器
文件頁(yè)數(shù): 10/105頁(yè)
文件大小: 449K
代理商: ISP1760
9397 750 13257
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 8 November 2004
10 of 105
Philips Semiconductors
ISP1760
Embedded Hi-Speed USB host controller
GND
A13
99
100
-
I
digital ground
address pin 13
input, 3.3 V tolerant
address pin 14
input, 3.3 V tolerant
address pin 15
input, 3.3 V tolerant
address pin 16
input, 3.3 V tolerant
digital voltage; 1.65 V to 3.6 V; connect a 100 nF decoupling
capacitor
address pin 17
input, 3.3 V tolerant
chip select signal that indicates the area being accessed; active
LOW
input, 3.3 V tolerant
read enable; active LOW
input, 3.3 V tolerant
write enable; active LOW
input, 3.3 V tolerant
digital ground
to indicate the presence of a minimum 3.3 V on pins 6 and 7
(open-drain); connect to V
CC(I/O)
through a 10 k
pull-up resistor
output pad, push-pull open-drain, 8 mA output drive, 5 V tolerant
not connected
Host Controller interrupt signal
output pad, 4 mA drive, 3.3 V tolerant
not connected
DMAC request for the Host Controller
output pad, 4 mA drive, 3.3 V tolerant
digital voltage; 1.65 V to 3.6 V; connect a 100 nF decoupling
capacitor
Host Controller DMA request acknowledgment; when not in use,
connect to V
CC(I/O)
through a 10 k
pull-up resistor
input, 3.3 V tolerant
connect to ground
core power output (1.8 V); internal 1.8 V for the digital core; used for
decoupling; connect a 100 nF capacitor
Host Controller suspend and wake-up; three-state suspend output
(active LOW) and wake-up input circuits are connected together
HIGH = output is three-state; ISP1760 is in suspend mode;
connect to V
CC(I/O)
through an external 10 k
pull-up resistor
LOW = output is LOW; ISP1760 is not in suspend mode.
output pad, open-drain, 4 mA output drive, 3.3 V tolerant
A14
101
I
A15
102
I
A16
103
I
V
CC(I/O)
104
P
A17
105
I
CS_N
106
I
RD_N
107
I
WR_N
108
I
GND
V
BAT_ON_N
109
110
-
OD
n.c.
IRQ
111
112
-
O
n.c.
DREQ
113
114
-
O
V
CC(I/O)
115
P
DACK
116
I
TEST
V
REG(1V8)
117
118
-
P
SUSPEND/
WAKEUP_
N
119
I/OD
Table 2:
Symbol
[1]
Pin description
…continued
Pin
Type
[2]
Description
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